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ADC31JB68EVM: ADC31JB68EVM

Corey Hirn
Prodigy 100 points

Part Number: ADC31JB68EVM

Hello,

I am looking for some help. I am using the ADC31JB68EVM in conjunction with the TSW14J56EVM. I have modified the ADC31JB68EVM for clock multiplier mode (PLL2 Only) by installing a 100MHz XO at Y3 and following the configurations required in section 5.1.1 of the ADCEVM user guide. I have also installed C51 and C67 (0.1 uF). I have configured the LMK on the ADCEVM to produce a 100Mhz clock on DCLKout8 (FMC_FPGA_DEVCLKA, FMC pins D4,D5)  The issue I am having is the TSW14J56EVM  D4  does not blink (Indicates presence of device clock from ADC EVM when blinking). The FMC_FPGA_DEVCLK pins (D4,D5) of the FMC connector on the ADC31JB68EVM are outputting the signal below.  

Can you recommend any trouble shooting ideas for identifying why the TSW14J56EVM is not recognizing the device clock?

Thank you.

  • 0
    TI__Genius 12780 points

    Hi Corey,

     Are you attempting to clock the ADC at 500 MHz? Can you please confirm that R43 and R50 are installed? Have you been able to verify that the DCLKOUT2 output of the LMK is making it all the way to the ADC clock pins? Are you able to probe the output data pins to see if they are toggling?

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 100 points

    Hello, I am attempting to clock the ADC at 200MHz DCLKOUT2 , 100MHz FPGA_DEVCLK on DCLKOUT8, and 15.625 FPGA_SYSREF on SDCLKout11. R43 and R50 are installed. I am able to verify the ADC is receiving a clock via probe and indication by reading the JESD_STATUS register and noting the CLK_RDY  bit is set high. is there a setting in the High speed data converter pro v4.90 software i need to adjust for these settings?

  • 0 in reply to Corey Hirn
    TI__Genius 12780 points

    Hi Corey,

    You will need to update the sampling frequency in the "ADC output data" field. See attachment for example (this is with the default clocking on the EVM).

    ADC31JB68EVM_Clocking.pptx

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 100 points

    Hello.

    I have tried setting the ADC output data to 200M. I verified a 200Mhz signal to the ADC and verified a 100Mhz signal on FPGA_DEVCLK line on the ADCEVM board. I get the warning message to check that the D4 light on the TS214J56 is blinking, and it is not. 

    What causes the D4 light to blink is it just a matching signal to the value set in the ADC output data field detected on the DEVCLK line. or does it also depend on JESD sync?

    Thanks.

  • 0 in reply to Corey Hirn
    TI__Genius 12780 points

    Hi Corey,

    Were you able to verify that the EVM is working properly in the default mode? Do you still require assistance with this issue?

    Best Regards,

    Dan