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ADS1299: Understanding SPI data communication

Part Number: ADS1299

When I trying to connect to ADS1299 with STM32 there is strange behavior:

I can't read registers after normal sequence of SDATAC and read commands.

I checked all signals on the line, timings tssc - its was normal, but ADS1299 always receive "0".

After some tryes I found that after write sequence for SDATAC before pushing high CS line I need to add delay or this command ignored.

I don't find description of this behaviour in documentation ("The SDATAC command cancels the Read Data Continuous mode. There are no SCLK rate restrictions for

this command, but the next command must wait for 4 tCLK cycles before completion." and same for multibyte command). Of course, I added this delay between SDATAC and registers reading, but this don't work.

If this proper ADS1299 operation and this will be the same for all single-byte write commands or my controller works incorrect ?

  • Hi Egor,

    Thanks for your post and welcome to the forum! 

    It's tough to say exactly what the issue is with the given information - it very well may be something with the STM32 which we cannot help with. 

    If you are waiting 4 tCLK cycles after sending SDATAC before pulling /CS high, there should not be an issue. Try using a scope to ensure that the timing is correct, perhaps the STM32 is pulling /CS high faster than it should be. 

    Additionally, if you haven't taken a look yet there is a checklist of items to consider when debugging SPI communication which can be found under the BIOFAQ post in my signature. 

  • Hi, Alexander.

    Thank you for response.

    Clk for ADS1299 come from internal source 2.048 MHz. Last clk cycle to cs rise delay ~ 480ns (according to datasheet, tCSSC min = 17ns). With oscilloscope below I read device ID 0x00. If I add delay before rising CS when send SDATAC I receive expected value 0x3E. It seems that absolutely not STM problem,and in slower controllers this delay just appears naturally

    SDATAC then read ID:

    SDATAC:

    Get ID:

  • Hi Egor,

    I'm assuming that Ch1 is SCLK, Ch4 is DIN, and Ch3 is /CS?

    One thing that may be causing an issue is the magnitude of the signals. 

    What kind of digital supply is the ADS1299 using? 

    There is a pretty significant looking over/undershoot on Ch4. If you look at the 7.1 Absolute Maximum Ratings in the datasheet you will see that the digital input should not exceed DVDD/DGND by more than +/-300mV, which I think the overshoot is. 

    I would recommend adding a small RC to this line. Place the R next to the STM32 and the C close to the ADS1299. In the neighborhood of 50ohm for the R and 10pF for the C. Let me know if this cleans up the signal.

  • I'm sorry. Seems that I mislead you a little. Last screens was only for showing timings.

    That spikes on screens are just oscilloscope artifacts.

    Property signal screens with spring on yellow probe:

    Clock with MOSI:

    Clock:

    Chip select

    DVDD

  • Hi Egor,

    Sorry for the delay, I'm planning to chat with the designers for this one. 

  • Hi, Alexander.

    OK. I wait for result.

    For now, I added 2 uS delay for single byte commands before rising chip select.

    Hope that other parts ADS1299 will work as expected.

  • Hi Egor,

    I missed this previously, but the minimum time after issuing a command to raising /CS is 4* tclk.

    Since you are using the internal clock with a frequency of 2.048MHz, one tclk is ~500nS. So waiting 2uS is the correct fix to your issue. 

    Take a look at tSCCS in the datasheet for further clarification.