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ADC12DJ3200QML-SP: SNR and clock jitter used in datasheet

Jonathan Geronga
Expert 7930 points
Part Number: ADC12DJ3200QML-SP

Hi Team,

We have a customer inquiry regarding figure 28 on page 29 of ADC12DJ3200QML-SP datasheet.
1. SNR is dependent on clock jitter. These are the measured results.
2. Do you know what the clock jitter is in these measurements?

Our customer would like to have a good jitter performance as the one used to generate the data in the datasheet when they select a clock.

Let me know if you have other information you need with our customer.

Thanks!

Jonathan

  • 0
    TI__Mastermind 30900 points

    Hi Jonathan,

    I am assuming from the figure, the clock would be 2Vpp differential. This would be around 42fSec of jitter presented to the ADC in order to achieve this SNR performance. I have a handy spreadsheet I can forward to the customer if interested. Just let me know.

    Keep in mind that SNR performance is not only a low noise/low jitter clock, but max slew also needs to be accounted for as well.

    Hope this helps.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    TI__Expert 7930 points

    Hi Rob,

    Thank you for this wonderful information.
    I will share this with our customer and let you know once there's another question or if this already resolves the question.

    Have a great day!

    Regards,

    Jonathan