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ADS7029-Q1: Serial Interface

Sadanori Kato
Guru 36520 points
Part Number: ADS7029-Q1

Hi,

I would like to confirm regarding the serial interface, so could you please give me your comments ?

Q1.
Is my understanding correct that SDO becomes "0" when /CS falls and SDO remains "0" until SCLK falls ?

Q2.
Is my understanding correct that the rising edge of SCLK is used when capturing data with FPGA since SDO data is switched in synchronization with the falling edge of SCLK after /CS signal falls ?

Q3.
Is my understanding correct that zero data of 2-bit is always added to the output data as a dummy bit ?

Q4.
Is my understanding correct that D0 from SDO is output at the 9th falling edge of SCLK ?

Q5.
Does SDO hold D0 even if the 10th SCLK fall ?

Q6.
Does SDO hold D0 even if the 11th SCLK fall ?

Q7.
Is D0 held until /CS goes high ?

Q8.
Can SCLK is kept high when /CS is low ?

Best regards,
Kato

  • 0
    TI__Mastermind 24940 points

    Hello

    1. The SDO will stay at the state it last was at until CS is asserted (becomes low), even until SCLK begins. The MSB is then outputted on the second SCLK falling edge. Section 8.3.4 of the datasheet provides more detail on this.

    2. Data is output from the device on the falling of SCLK, thus the host should read the data on the rising edge of SCLK

    3. There are two leading zeros in a data transfer frame. Section 8.3.4 of the datasheet provides more detail on this

    4. Correct

    5. SDO goes low after the 10th SCLK falling edge section 8.4.12, offset Calibration during normal operation provides more detail on this

    6. SDO goes low after the 10th SCLK falling edge and stays low. section 8.4.12, offset Calibration during normal operation provides more detail on this

    7. SDO goes back to tri-state after CS rises, which means it will hold the last it was at. section 8.4.12, offset Calibration during normal operation provides more detail on this

    8. Are you referring to clock stretching, where SCLK will not follow a consistent period? I have not tested this on the device, but it seems this is a violation of the timing requirements.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Guru 36520 points

    Hi Cynthia-san,

    Thank you for the information.

    I understand and will contact you if I have additional questions from our customer.

    Best regards,
    Kato