• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 328 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADC12D1800: ADC Test Pattern

ADC12D1800: ADC12D1800

sangeetha s1
Prodigy 110 points
Part Number: ADC12D1800

Dear Team,

We are using ADC12D1800 in our design ,following are the specifications.

ADC input frequency : DC-500MHz

Sampling mode : Non-Des mode

Sampling frequency : 1.35GHz

 

We have designed two boards one board is working fine with DDRPh=0 deg,but the second board is not working same phase(ADC sampled data is corrupted).

when we changed DDRPH=90deg it is working .ADC sampled data is correct,

May i know whether problem with sampling clock or any other constraint?

 

Kindly give us some suggestions to solve the same.

  • 0
    TI__Mastermind 38150 points

    Hi Sangeetha,

    It maybe possible that the data to dclk timing is on the edge. Therefore, on one board it works for 0phase and the other board works with 90phase. Can you see if the board that works for 0phase works, with 90phase as well?

    Do the two boards have two different connections to the FPGA or digital receiver? Any skew between the two boards or their digital receiver side can also cause timing delays which will require more timing margin.

    Hope this helps.

    Regards,

    Rob