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I am seeing a fixed DC offset in the output of adc when it is set in LVCMOS mode vs when it is set in LVDS output mode. When I give input as sine wave of 10dBm 1MHz frequency, the output of LVCMOS mode is centered at 0 . However, when the adc output mode is set as LVCMOS, the output comes out above (2^13), though the shape is retained correctly. I am suspecting that the parallel LVCMOS mode is not removing the dc offset.
Also when I give no input to channel A, I am expecting the lower 2-3 bits to be triggered rest all should be 0. This is observed for LVDS mode, but in CMOS mode, 2-3 bits are triggered and rest all are fixed at HIGH.
Is there a way to overcome this issue or some register settings for ADC to be set. I have already tried 'Enable Offset Correction' for ADC but did not work.
Prem,
Please see page 15 of the ADS62P49 datasheet at the link posted below. You will see that you have to selectively change the voltage applied to pins SCLK and SEN depending on which interface (LVDS or CMOS) and data format (2's complement or Offset binary) you are using. Verify that you are correctly setting the voltages as shown in Table 5 and Table 6 and verify that you get the expected results.
Yusuf
Prem,
As mentioned in the prior message, on page 15 of the datasheet, instructions are shown for how to configure in parallel mode. Have you referenced them? First sentence states that RESET must be held high for parallel mode. have you confirmed this?
Yusuf
Prem,
You can also adjust data format by properly programming register address x50. You can choose whether output data is formatted as 2's complement or offset binary as shown below. Reference page 25 of the datasheet.
Yusuf
