Other Parts Discussed in Thread: ADS54J60,
I'm looking at a new design with multiple ADS54J60 ADCs running in Subclass 1 and I'm wondering what the guidance is for trace length matching SYSREF and the SERDES PLL ref clk to the FPGA?
I know how important it is to match the trace lengths for the SYSREFs and device clocks to the data converters, but what about to the FPGA?
Edit: I should've put the clock generator I'm using rather than the ADC. I will be clocking the ADCs and FPGA with the LMK04828.
