We've built 7 pieces of a new design that uses 2 ads1278s each. We have had several ADS1278s that developed internal shorts between AVDD and AGND. With so few boards, I can't help wondering if I’ve made a design flaw.
One candidate is the power up sequence. The data sheet asks to have DVDD (1.8V) before IOVDD (3.3) before AVDD (5.0V).
But another part in my systems requires the larger supplies to come up before the smaller supplies. So 5.0 before 3.3 before 1.8.
In order to comply with these opposing requirements, I found a cute part that controls the power up sequence and ensures that all three supplies ramp up together until 1.8V, and that 3.3 and 5 ramp up together until 3.3V and then 5 by itself.
The data sheet shows that DVDD is before IOVDD is before AVDD, but it doesn’t give a required minimum time delay. Indeed it allows DVDD and IOVDD to come up together if they are wired together. Is there a minimum time delay?
Would violating the power up sequence cause permanent damage, or just inaccurate operation until an ADCSYNC resynchronized the internal logic?
Another likely candidate for damage was the analog input pins, but the op-amps driving the analog inputs are powered by the same AVDD as the ADC. The op-amp inputs are all diode clamped to the rails.
Has anyone else experienced similar failures? What did the problem turn out to be?
