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Hi team,
How to understand the following sentence mentioned in application report "SLAA013"?
"The limit of a 1/2 LSB differential linearity error is a missing code condition which is equivalent to a reduction of 1 bit of resolution
and hence a reduction of 6 dB in the SNR"
Why 1/2 LSB DNL equals to a reduction of 1bit resolution rather than 1LSB DNL?
Hi Charles,
Thank you for your post. I've edited the title as this question can apply to all data converters in general.
Of course, data converters have a finite number of codes in their transfer function, so there is a possible range of input voltages that could produce the same code in an ADC. The ideal voltage is at the center of the code "step." Each step is 1/2 LSB away from transitioning to the previous or next code (hence +/- 1/2 LSB from the ideal input voltage). If your non-linear error is greater than 1/2 LSB, this is enough to cause the ADC code to transition to the previous or next code, depending on the sign of the error.
Regards,