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Hello,
Does ADS4122 support direct clocking or does the asic alter the clock signal internal (e.g. PLL, DCS etc.)? In figure 93 of datasheet, there is an input buffer with a branch directly to the sampling circuit visible, while the second connection goes to an internal clock generator.
Is this clock generator just for sync of the output clk needed and for proper timing of the SC circuits needed (charge injection etc. ) or is there a complete clock recovery?
Dear Jim,
Thanks for your fast response. So your answer means that the sample and hold stage works on the input clock directly (except internal buffering) and the other internal clocks are built out of the input clock.
My apllication wants to sample exactly at the time point of the external source. However, this clock source is not a stable (non-aequidistant sampling) signal. What happens with the internal- and output clock (For a PLL circuit this would be very bad as there is the loop...)?
Regards,
Gecko
Jim,
Unfortunately I had not the time to generate a waveform diagram. However, it is a chirp signal with changing amplitude. For example is the frequency of the signal increasing during the record. At the same time, the amplitude gets first bigger and then again smaller. The duty cycle requirements are hold, there are no aprupt jumps in frequency/amplitude.
Regards,
Gecko
Jim,
It is the clock input. The clock source is generated from a physical process. Our data input is generated by the same process and we like to sample the data at the time points given by the clock signal.
I know that it is hard to answer the question. However, my thought was if we can sample (with the S/H stage) at the given time points and then process the other stages with a unprecise clock we would have what we need. Our main concern is that there is a PLL or other loop which has a problem with change in clock frequency.
Regards,
Gecko
Gecko,
There is a duty cycle, phase, common mode and amplitude requirement for the clock input. To me it sounds like you are possibly violating all of these. If this is true for any one of these, there is no guarantee this device will work properly.
Regards,
Jim
Jim,
duty cycle, common mode and amplitude requirements are hold. As the frequency change the phase requirement may be a problem. I am not sure, if I understand you right. Can you tell me in which chapter I find the phase requirements in datasheet?
Tanks.
Regards,
Gecko
Jim,
Thanks for the referencing.I have already considered these points. As I hold these requirements, I should be able to use this device. Thre might be an issue with the performance parameters as SNR etc. as I have a non-ideal clock (The change in frequency can somehow be seen as a jitter). I guess I have to setup such a system and do my own measurements. Thanks for your support.
Best Regards,
Gecko