ADC12DL3200: DxCLK default output

User,

What is the amplitude of the clock input at the ADC? Is this within spec of the data sheet?

Regards,

Jim 

User,

The 2.12MHz clock is possibly due to the “self-toggling” clock in the ADC that is there to prevent asymmetric aging when the ADC is in power-down mode.

Can you verify the logic state of the power down pin of the ADC? Also verify the power down register is not set to power down mode.

Regards,

Jim

Hi Jim

Thanks for your response.

my ADC is on a seperated FMC card, on FMC card, an external 3GHz clock input from SMA connector, pass through a balun then AC coupled pass into ADC.

this FMC card could be mounted on carrier card via FMC connector, then the ADC connect to xilinx KU115 FPGA on carrier card. 

I tried below actions:

1, check design, the PD pin R1 connect to GND via a 0 ohm resistor. read out reg 0x002 = 0;

2, DxCLK can be disabled by writing reg 0x002=3(power down ADC), or disable LVDS_EN by writing 0x200 = 0; NO 2.12MHz present on DxCLK after these regs writen.

3, just seperately power on  the FMC card, no external 3GHz clock input, no FPGA connection. the i still can get the 2.12MHz on DxCLK once power up.

4, at the beginning few seconds of power up, the data bus has data toggling, but stucks at 0 after ~5 seconds. but occasionally the data bus also driving output 2.12MHz clock after data toggling period.

5, driving the 3GHz clock with R&S SG at 7dBm, the clock amplitude is ~1.2Vpp(I checked with differential probe at AC capacitors). all the same behavior as above.

6,  double check Chip ID, reg 0x00c= 0x51,  reg 0x00D = 0x04, is that correct?

looking forward your guidance... thanks

User,

The 1.1V supply going to VA11 and VD11 are critical to the operation of the clock. Make sure these supplies are at the correct voltage level and can provide enough current.

As a sanity check, try running the ADC at a much slower sampling rate.

Regards,

Jim 

hi,

the power part topology exactly followed datasheet figure 179, and i checked the supplies voltage meets the requirement,and the VA11&VD11 is ~2ms later than VA19 which meet the power sequence as well.

also i tried to change the ADC clock to 1GHz, but nothing helps. the same as before, the DxCLK is still driving output 2.12MHz , just the same as no external CLK input enabled.

is there any other shadow register rather than datasheet stated register map to check the ADC status?

BR.

User,

Is there any way to measure the power consumption of the device?

Can you send us your schematic to review?

Regards,

Jim

Hi

enclosed the schematic for review and power VA1.1& VA1.9 measurement.

BR.

fmc.pdf

User,

The design team is looking into this.

Regards,

Jim

User,

The EVM schematic from Mini-Circuits (attached) which uses the same transformer you are using for the clock input is wired differently than what you have. Have you verified that both CLK inputs are correct at the ADC? Can you read the temp sensor inside the part? is this changing over time after power up and a clock present?

Regards,

Jim

 WTB-654+_P02.pdf

Hi,

1, the ADC clock input is correct, i made a measurement at the AC capacitors which the closest to ADC pin as below picture.

2,the DxCLK output always present once power up, also present even if no 3GHz reference clock providing. and never change when power cycling or register configuration. the DxCLK shown as below picture, the amplitude is ~2V.

3, i can read/write all register, also i can disable the DxCLK by write reg 0x200=0.

4, now the total power consumption is about 0.25A*12V = 3W.

pic1: ADC 3GHz ref clk close to ADC CLK IN pin.

pic 2: DxCLK output

User,

You mention "now the total power consumption is about 0.25A*12V = 3W". How much of this is from the ADC? Does this change when you turn off the clock? Have you tried running with a slower clock? Have you tried any of the user defined test patterns to see if the data coming out was correct?

Regards,

Jim

Hi,

i design the power topology as datasheet Figure 179, now the 12V import consume 0.25A, that's for ADC and all the DCDC regulators&LDO loss. no other components use this 12V power rail. it's always 0.25A, no change while power cycling.

i tried to change a slower clock 2GHz and 1GHz, always the same 2.13MHz output at DxCLK.

i tried to config ADC as datasheet chapter 8.3, also set user defined test pattern, but the problem is since no correct DxCLK, i can't bring up the LVDS interface in FPGA side, the PLL in FPGA cant get lock, so i can't extract any data...

since the DxCLK output behave like 'default status' of ADC, is any such as 'shadow register' or any suggestion to check the ADC status?

Best Regards.

User,

From your answers, I still could not tell if the power changed with the clock present or removed.

Regards,

Jim

Hi

the power consumption doesn't change along with clock present or removed.

BR.

User,

Applying clk to the part should change the power level on VA11 and VD11 significantly.

Please try to set the part into powerdown mode via spi and see if the power changes at least for powerdown mode compared to normal operation.

Looking into the datasheet of the regulators the ones you are using have an efficiency below 80% for 12V input. Based on the power consumption of the 12V supply at 3W would mean the part can max consume 2.4W. If clk is applied the power of the ADCDL3200 should be above 3W.

The amplitude for DxCLK seems too high. Was this measured with an 100 OHM external termination or without?

If the termination resistor was in place something is wrong with the signal level.

Here are a couple of other things to try to narrow down the problem based on the design team’s input:

1. Provide the SPI writes to the part

2. Try to measure DxCLK output without any SPI writes to the part. Just power it up.

3. Check register 0x7D (it should be 0x80) – check 1s after power up

4. Check register 0x270 (should be 0x01) – check 1s after power up

5. Check register 0x2A (should be 0x00) – check 1s after power up

6. Set register 0x201 to 0x00  and measure the DCLK frequency (should be doubled)

7. Measure the IV-Characteristics of the CLK pins wrt chip GND

8. Measure the differential resistance between the CLK pins

9. Measure the DC voltage on the CLK pins with respect to chip GND

10. Continuously write 0x2B7 to 0xFF and then to 0x00 (the DXCLK output should have glitches with the frequency of the SPI write)

11. Is it possible to try a different part and/or different board?

Everybody in the design team is suspecting the CLK path as the issue. Either a chip fault or the part not correctly connected to the CLK source (e.g. soldering issue)

Regards,

Jim

Hi

Thank you all, i would like to update the status:

1) when i test the power consumption of FMC card only(NO FPGA connection), it's 0.25A*12V; when i mount the FMC card on carrier card, FPGA write register 0x2=3 to set ADC into power down mode, the current decrease 0.33A on 12V power rail.

2)last time i tested the DxCLK without 100 ohm termination, the amplitude is 800mV when 100 ohm terminated on DxCLK.

all the APs update inline:

1. Provide the SPI writes to the part

2. Try to measure DxCLK output without any SPI writes to the part. Just power it up.

   1. the amplitude is 800mV when 100 ohm terminated. the DxCLK frequency remains at 2.13MHz after power up.

3. Check register 0x7D (it should be 0x80) – check 1s after power up

   1. yes, it's 0x80.

4. Check register 0x270 (should be 0x01) – check 1s after power up

   1. yes it's 0x01.

5. Check register 0x2A (should be 0x00) – check 1s after power up

   1. yes it's 0x0.

6. Set register 0x201 to 0x00  and measure the DCLK frequency (should be doubled)

   1. yes, the frequency will double to 4.26MHz when 0x201 set to 0x00.

7. Measure the IV-Characteristics of the CLK pins wrt chip GND

   1. sorry i can't got the mean of this case. could you explain more details on this one?

8. Measure the differential resistance between the CLK pins

   1. the differential resistance is 79.8 ohm, i measured with a multi-meter at the CLK AC capacitors after power up.

9. Measure the DC voltage on the CLK pins with respect to chip GND

   1. it's only ~4mV.  measure point: AC capacitors pad which closed to ADC.(here i suppose it should be 0.3V from spec?), and i confirm that the 1.1V and 1.9V voltage is 1.098V and 1.878V at via close to ADC pin.

10. Continuously write 0x2B7 to 0xFF and then to 0x00 (the DXCLK output should have glitches with the frequency of the SPI write)

    1. yes i can get the the CLK shift while SPI write.

11. Is it possible to try a different part and/or different board?

    1. i have 2 FMC boards, and they are the same phenomenon.

it seems that the common mode voltage on CLK is different from spec?

but the HW design is AC coupled CLK input. register 0x2a is set to 0x0 which DEVCLK_LVPECL_EN = 0 means self bias used.

thanks for your support.

BR.

User,

 See new comments added to yours below.

Regards,

Jim

1. Provide the SPI writes to the part

   • I still would like to see what normally is written to the part at start-up

1. Measure the IV-Characteristics of the CLK pins wrt chip GND

   • sorry I can't got the mean of this case. could you explain more details on this one?

     1. Power up the part.

     2. Short the positive and negative CLK input to your + connector of a voltage source

     3. Connect the – connector of your voltage source to AGND

     4. Sweep the voltage on your voltage source from -0.5V to 1.6V

     5. Measure the current flowing out of your voltage source

     6. Repeat measurement with + connector of the voltage source only connected to CLK+ pin of the chip

     7. Repeat measurement with + connector of the voltage source only connected to CLK- pin of the chip

2. Measure the differential resistance between the CLK pins

   • the differential resistance is 79.8 ohm, i measured with a multi-meter at the CLK AC capacitors after power up.

     1. 79.8 Ohm seems to be low. Could you please don’t power up your board and measure again? Make sure your multi-meter is not applying more than 0.5V across the terminals, otherwise the ESD diodes will turn on.

3. Measure the DC voltage on the CLK pins with respect to chip GND

   • it's only ~4mV.  measure point: AC capacitors pad which closed to ADC.(here i suppose it should be 0.3V from spec?), and i confirm that the 1.1V and 1.9V voltage is 1.098V and 1.878V at via close to ADC pin.

     1. Yes it should be ~0.3V

Would it be possible to get a picture of the board layout? Would be sufficient to see the area between the ADC and the AC Caps for the clk.

Hi

1, the initial set up as below txt file:

addr          reg

0x0           0xb0
0x0           0x30
0x200         0x0
0x61          0x0
0x201         0x5
0x204         0x2
0x206         0xf
0x62          0xa
0x6b          0x0
0x180         0x11
0x181         0x1
0x182         0x22
0x183         0x2
0x184         0x33
0x185         0x3
0x186         0x44
0x187         0x4
0x188         0x55
0x189         0x5
0x18a         0x66
0x18b         0x6
0x18c         0x77
0x18d         0x7
0x18e         0x88
0x18f         0x8
0x205         0x11
0x190         0x0
0x213         0x87
0x200         0x1
0x6c          0x0
0x6c          0x1
0x6c          0x0

2, I-V character wrt GND as below pic:

3, the differential resistance is 142.2ohm when power off, and 79ohm when power on and CLK input removed.(ensure less than 0.5V differential voltage) 

4, shall we grasp this clue and dig in to see why it's not 0.3V?

5, the AC CAP is closed to ADC as possible as below pic:

Thanks and Best Regards.

Hi

I was shocked from this reply and finally i realized that i made such a stupid mistake: i mis-connected the ADC RF input and clock input..  that's why i am failed to get the clock output on DxCLK. now everything works well now.

even feeling a little bit frustrated on such kind of mistake, but that is part of work and life. anyhow, here i would sincerely appreciate all of you TI guys help me to find the root cause out. thanks for your professionalism, insistence, and patience! really great support! you guys made my day. now just take a cup of coffee and chat with your colleagues: hejhej~ i got a funny case, here is a nerd who made such a stupid mistake blabla,  :-)