In single channel mode, data sheet recommends using INA+/- input (instead of INB) and data is sampled at rising and falling edges of CLK+/-. Therefore, if I want to sample at 1 Gsps in single channel mode, using only INA+/- (INB+/- is not connected), I would set CLK+/- = 500MHz, right? Also, while in single channel mode, using only channel A ADC, why is does Table 21, JMODE0, shows DB0-DB3 as the odd samples (S1,S3...) from the negative edge of CLK+/-? In single channel mode, channel B ADC is not used, why does it show up as the JESD204B output data?
If I run the ADC12DJ3200 in dual channel mode, CLK+/- = 1 GHz, and only driving channel A (INA+/-) while channel B is not connected, then process the JESD204B, link A only. Is this the same as running in single channel mode, CLK+/- = 0.5 GHz, only driving channel A, and processing JESD204B, link A only?
Is dual channel mode sampling both A and B channels on the same rising edge of the input Clk+/-? The sampling instance of A relative to B is not 180 degrees out of phase from each other, right?
TADJ_A and TADJ_B are 8 bit registers that I'm assuming are defaulted to the same value at the factory. If you change one of these values, you can change the sampling instance of ADC A relative to ADC B. How are these 8 bit values defined? Is it a delay value relative to CLK+/- phase?
