ADS54J66EVM: Wrong ADC sample data. Not receiving sine wave

Thank you, Jim for your quick response. I appreciate your time and help. I set SYSREF to 2.4MHz by changing the sysref divider value to 1024 (VCO 0 frequency is 2457.6MHz). I tried the ramp pattern and observed occasional erratic behavior. The ramp drops midway while ramping and stays low for a few cycles before ramping again. 

I would also like to confirm the ADC sample data demapping with you. I am demapping 32bit JESD data frame as below -  

lane0_tailbits1  <= rxdata[1:0];                                 //0,1 are tail bits                                        
     
lane0_sample1  <= {rxdata[15:8],    rxdata[7:2]};                  
     
lane0_tailbits0  <= rxdata[17:16];                            //16, 17 are tail bits
     
lane0_sample0 <= {rxdata[31:24], rxdata[23:18]};

Rajk,

The ADC sampling map is correct.

See the ramp pattern file attached.  This is data from our TSW14J56EVM, which is a capture/pattern generator board that TI sells to support this ADC EVM. You will notice this test pattern does not generate the perfect ramp. There is a small dead spot at the end of each complete cycle. 

Regards,

Jim

2783.ADS54J66_ramp_test_Mode_8.pptx

Hi Jim,

Thank you for your help. As per your suggestion, I lowered the input frequency to 20MHz at 5dbm but did not observe a sine wave on the FPGA. I connected the signal generator to input A and left B, C and D disconnected. I also probed the output of the transformer between SMA connector and ADC on the evaluation board and could see 20MHz sine wave there. I used the configuration file you attached in your reply above.

Rajk,

After power and clocks are provided to the ADC, press the reset button on the board before loading the ADC registers. Try lowering the frequency of the input  even more and use the ILA tool to look at the individual bits. This may provide clues to see how the data ordering is being processed. 

Regards,

Jim

Hi Jim,

I followed your suggestion and lowered the input frequency to 1MHz on input A of the ADC. I left inputs B, C and D disconnected. I observed the data coming out on the AXI stream bus of JESD receiver module. I noticed, if I swap the upper and lower byte of lower 16 bits [15:0], the control bits or tails bits are present at bit 7 and bit 6. I assumed bits 7 and 6 are tail bits because they are always 0.

If I remove bits 7 and 6, I see a cleaner sine wave.

When I observed the upper 16 bits [31:16], I noticed bit 20 is always zero. I assumed bit 20 and 21 to be tail bits and removed them.




After removing bits 20 and 21 and swapping the bits (based on my observation of [15:0]) as shown in the attached photo, I see a cleaner sine wave.



However, the upper 16 bits [31:16] sample is not as clean as the lower 16bits [15:0] sample. I believe it may be because bits [31:28] have same value.



This frame mapping looks significantly different than the ADC datasheet and PG066 AXI stream data mapping. I have also noticed a pattern on the 128bit AXI stream data bus, where bits 6, 20, 34, 48, 62, 76,90, 104, 118 are 0 (every 14th bit is 0 starting from bit 6). I assumed these are control bits along with the next adjacent bit. eg - bit 6 and 7, bit 20 and 21 and so on.  

8585.ZC706 ADS54J66 4421 Setup.pptxRajk,

We have tested this EVM in the 4421 mode using a ZC706 with our TSW14J10EVM. The source code for this project can be downloaded from the TSW14J10EVM product folder on the TI website. See if this helps with your issue.

Regards,

Jim

Thank you Jim for your continued help. After investigating further, I found the GT data coming out of the JESD PHY module has the control bits in the correct position but somehow it was getting incorrectly mapped on the AXI Stream data bus.

 
The tail bits in the lower 16 bits [15:0] are 8 and 9. I swapped the upper and lower bytes and removed bits 8 and 9 to get a clean sine wave. Is it correct tails bits are bits 8 and 9 for [15:0]sample and bits 24 and 25 for  [31:16] sample?