ADS54J66: JESD loses sync intermittently

Rajk,

SYSREF is normally turned off once the link is established to prevent any possible spurs from the switching of this clock. Once turned off, it only needs to be turned back on if SYNC is lost. You can turn off the alignment characters coming out of the ADC. Have you tried this?

Regards,

Jim  

Hi Jim,

Thank you for the information. I have the lane align and frame align bits of register 0x6900 set to 0. Are there any other registers I'm missing ?

Please find the configuration file I'm using attached here.ADS_4421_TI_Ticket.cfg

ADS_4421_TI_Ticket_New.cfgRajk,

Try using the attached config file.

Regards,

Jim

Hi Jim,

Thank you for the configuration file. I configured the ADC with this configuration file and tested it with different input frequencies at different levels. eg - 644MHz, 1GHz, 10MHz, 20MHz, 100MHz, etc and at 1dbm, 2dbm, 3dbm, 4dbm. The JESD link still loses sync 2-3 hours after establishing it. I checked the JESD link error registers in the FPGA and they were all zero. Do you have any suggestion to resolve this ?    

RajK,

Is SYSREF running the entire time? If so, stop it after the link is configured. Another thing to try is a different clock source to the ADC. Is power stable? 

Regards,

Jim

Hi Jim,

Sysref is pulsed and only triggered to establish sync. The onboard 122.88MHz oscillator is bypassed and I have connected an external clock 337.866MHz to J12. I followed the instructions in SLAU641D. I removed R62, C169, C121 and installed R60, R61, C92 on the evaluation board ADS54J66EVM. JP2 (XO_PWR) is left open to turn off the onboard oscillator to avoid crosstalk. I am using the power adapter that came with the evaluation board as power source.


I have observed JESD link loses sync in both cases (using onboard oscillator and external clock). I have also noticed when JESD link loses sync, power cycling the evaluation board does not help and the FPGA does not detect 0xBCBC characters. Only after I re-program the FPGA, I can re-establish the link.  Do you have suggestions to check stability of power source ?

RajK,

When you used on-board clocking, what was the status of LED D3 (PLL2 lock) when you lost SYNC? This LED should be on at all times indicating the VCO inside the LMK is locked to the on-board VCXO. 

If you still want to use an external clock, please also make the following changes:

Remove R102 and C80.

Install a 0 Ohm resistor for C82 and a 0.1uF cap for R77. Verify the clock amplitude is at the correct level at the LMK input.

Connect an external power supply if available and monitor the current of the ADC EVM before and after the issue. If you think there may be an issue with the board, we can have you request for a replacement board.

Regards,

Jim

Hi Jim,

I made the changes you recommended and the current is stable before and after. Not sure what is still causing the issue. I would like to request  a replacement evaluation board. Could you please let me know the procedure for that. Thank you and I appreciate your time and help.

Thank you for the link, Jim. I have started the replacement process. 

I have a question regarding the operation of ADS54J66 when sync has been established. Is the link supposed to remain stable and in sync as long as the power supply and clock are stable ? Will it remain stable for over 24hours or longer ? Are there other factors that affect the link  ? We are evaluating its long term performance and stability before going ahead with our custom PCB production.

We are migrating from ADS6442 to ADS54J66 and studying the changes in design we will have to make to ensure smooth transition. In our experience with ADS6442, we configured its registers at the beginning of operation and did not have to modify them later during runtime. When we migrate to ADS54J66, we will have to take JESD link stability into account during runtime. Our design requires unhindered continuous operation for over 24hours. We want to test ADS54J66 JESD link for its long term continuous operation without losing sync. Do you have recommendations for us when we are laying out our custom PCB to ensure long term stability ? We have the evaluation board schematic and gerber files as reference. Also, do you have recommendations for the digital side of the design ? Thank you      

RajK,

The SYNC should stay stable as long as power and clocks are stable. Should last for days if not months. A glitch on a reset line could cause the link to go down.

If you have poor signal integrity that degrades over temperature, this could be an issue. Design guidelines are attached.

Regards,

Jim

3644.High Speed Serial Link Layout Recommendations.pptx0284.JESD204B Physical Layer.pptx3603.Techniques for High Speed PCB Layout.docx

Hi Jim,

I have an update. I received a replacement board and I made same modifications on it as you detailed in your previous response. These modifications were to bypass the onboard oscillator and use J12 for locking PLL2 to external reference clock. I have experienced the same issue where rx_sync goes low after being high for about 2hours.

I have spent significant time in debugging this issue but haven't seen any progress. Here are my findings -

Test Setup 

FPGA JESD RX - ZCU102 HPC 1, Line rate = 6.546Gbps, LMFS = 4421, CPLL, RefClk = 163.65MHz, Sysref always ON, GTHE4 location - X0Y15, X0Y14, X0Y13, X0Y12, Coreclk = 163.65MHz. "Shared logic in core", K = 32

LMK - Sysref = 2.557MHz, Ext Ref clk = 337.8666MHz, VCO = 2618.466667MHz

ADC - Sampling Freq = 327.3083MHz, LMFS = 4421, Mode 8, No analog signals connected to ADC input.

I'm attaching the ADC and LMK configuration files here. 
lmkadc337p866.cfg

1401.ADS_4421_TI_Ticket_New.cfg 
I have been testing this setup on Xilinx ZCU102 and as a sanity check of ZCU102 board being defective, I also tested this setup on Xilinx KCU105. With KCU 105 I observed the same issue. I am attaching the sync loss screenshot here.



As per your guideline, to monitor the EVM board power, I connected a programmable DC power supply to it.

Current at startup - 0.895A
Current before sync - 1.078A
Current while in sync - 1.085A (this is stable while in sync)
Current after sync loss - 1.078A

The block diagram is here 


The Initialization sequence is - 

1) Program LMK and wait for PLL2 Lock.

2) Program FPGA

3) Send 1 to rx_reset pin of the JESD RX module (highlighted in above photo). KCU_JESD_Reset module is custom AXI module to reset and monitor JESD module.

4) Send 0 to rx_reset pin of JESD RX module.

5) Write 0x2 to JESD RX AXI register 0x04 (fixed reset) to hold the JESD core in reset.

6) Program ADC registers.

7) Clear JESD core reset. After clearing reset, the GT lanes start seeing 0xBCBC characters.

8) Trigger Sysref

9) rx_sync  goes high indicating sync established. (see below photo)



During testing, I have observed, rx_sync  remains high for approx. between 2hr 05mins and 2hr 25mins. This time is same for ZCU102 and KCU105. I have tested this at least 20 times and the time for which rx_sync is high, is same between 2hr5min and 2hr25min. 

I suspected three causes for this issue - 

1) Power 

To ensure stable power supply, I connected the EVM board to an external DC power supply.

2) Clock

To ensure stable clock I have monitored the PLL2 lock LED and it has remained ON before, during and after sync. 

3) Signal Integrity

I have tested two different ADS54J66EVM boards and two FPGA boards (ZCU102 and KCU105).

Even after this, the problem remains. I would like to confirm whether the initialization sequence mentioned above is correct. You also mentioned about a possible glitch in the reset. I monitored the reset signal and did not find any unusual activity on it. Is there anything I am missing or doing incorrectly ?

I appreciate your guidance and time.