I have some questions about the serial interface.
1.
1.
The chapter "8.3.4 Serial Interface" in the data sheet "ads7029-q1.pdf" (Rev. SBAS811 - JANUARY 2017) looks to me like a copy of a 12 ADC.
Is it really the way it is written in the text, or is "Figure 1 and 33: Time diagram" the reference for designing an interface?
I ask because some ADC families have the same length of the result register, regardless of 8/10/12 ... bit-wide ADCs. They fill the missing bits with 0.
2.
Is the number of clocks / bits in the chapters "8.4.1.1 Offset Calibration on Power-Up" and "8.4.1.2 Offset Calibration During Normal Operation" correct?
Is it really the way it is written in the text, or is "Figure 1 and 33: Time diagram" the reference for designing an interface?
I ask because some ADC families have the same length of the result register, regardless of 8/10/12 ... bit-wide ADCs. They fill the missing bits with 0.
2.
Is the number of clocks / bits in the chapters "8.4.1.1 Offset Calibration on Power-Up" and "8.4.1.2 Offset Calibration During Normal Operation" correct?
