I have 2 analog differential inputs, and 2 RTDs. I'd like to continuously scan the 4 channels at the 2KSPS rate (i.e. tie START high, single mode DOUT). What I'm not sure about is the SPI flow.
The datasheet in section 9.6.3 says "With the START pin held high, the ADC converts the selected input channels continuously.", but does this mean that when DRDY goes low, you read the result of one channel (RDATA or RDATAC?) while simultaneously sending the configuration bytes for the next read (WREG MUX0, WREG SYS0's PGA)?
And these 40 SCLKs (5 bytes * 8) happen before the next DRDY goes high, with the CSN around the first 24-bit read, and then each of the WREG writes?
