Part Number: ADS54J66
hello,
we are currently working on ads54j66 in default 4421 mode 8 configuration.Initially we are trying to establish a link between IC and FPGA so we are sending test pattern (counter data) from ADC.
configuration are ;
CLocks (LMK04826B ) ; ADC clock : 312.5 MHz sysref : 4.88 MHz mode : 4421 mode 8(un-decimated)
THE above configuration were simulated on ADS54J66 EVM board and CUSTOM BOARD board. the result are as shown below
IMAGE 1 : EVALUATION BOARD
2 : CUSTOM BOARD
for both board LMK configuration, ADC configuration and FPGA configuration are same.
QUESTIONS:
a) as shown in the second image the counter data is not proper why? when we configure configure ADC with all zeros test pattern,all ones test pattern and custom patterns ,the output of both boards are same.
b) sometime the counter data is repeating for 3 to clock cycles and den incrementing for sometime and so on.since the behavior is so random we are unable to get to an conclusion. so what are registers which help us to Debug the issue?
thank you
