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Original question:

DAC5681Z: DAC5681z

DAC5681Z: Data sampling rate vs Interpolation

Enrique Rivera
Prodigy 60 points

Part Number: DAC5681Z

Hello,

We have a problem for understanding of the relationship between the input data rate (input clock 250MHz) of FPGA and the sample rate of DAC (1GHz) with interpolation. We saw the example provided by the datasheet (page 20 and 21), we understood that the ratio between these two parameters (input data rate of FPGA and the sample rate of DAC) should be 1/4 to have a transition from 4 parallel samples to 4 serial samples without interpolation. What if we apply x2 or x4 interpolation in the DAC ? Should we keep the same ratio 1/4, or change the ratio to 1/8 (x2 interpolation) or 1/16 (x4 interpolation) ?

Thanks in advance,

BR,

Enrique

  • 0
    TI__Mastermind 18095 points

    Yes the ratio is between the data rate and the FPGA SerDes rate.  So effectively the interpolation factor is included when dividing down from the sample clock.  For example, with a 1 GSPS clock, 2x interpolation, you would divide the sample clock by (2 * 4 =) 8 to the FPGA.

    --RJH