• State TI Thinks Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 6 answers
  • Subscribers 48 subscribers
  • Views 471 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AFE5809EVM: AFE5809 GUI Launch problem

AFE5809: Regarding sampling clock after decimation

charan teja
Prodigy 30 points

Part Number: AFE5809

hi TI team,

We are trying to configure the AFE with 10 MHz Fs, operating in a 16 bit mode..

When we use demodulation technique with decimation factor 32, do we get 10 MHz Fs to the fpga or 10MHz/32. 

Please help with the procedure to verify the filter coefficients.

Kindly respond..

regards,

B.charan teja. 

  • 0
    TI__Genius 12025 points

    Hi,

    Thanks for using AFE5809 device.

    Yes, for your question please refer to AFE5809 Datasheet page 44 section 3.

    Down-sampler gives out 1 sample followed by M - 1 samples zeros.

    Thank you!

  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi,

    Also in your case the decimation factor M = 32.

    Thank you!

  • 0 in reply to Chen Kung
    Prodigy 30 points

    Hi TI team,

    thank you  for your response..

    i am facing one more issue, when i checked with test patterns without decimation   here Fs= 10 MHz, 

    we are using 96 channel data acquisition i.e 12 adc's 

    i am getting synchronisation with test patterns ramp, but i am not getting when i changed the mode to toggle 1 and 0's pattern.

  • 0 in reply to charan teja
    TI__Genius 12025 points

    Hi,

    Thank you for letting us know.

    When you are using multiple AFE5809 devices,

    please consider how to synchronize their Clock input signals together

    (Please look at the AFE5809 Datasheet Page 95 Figure 109)

    and also TX_SYNC_IN input signal (plus TSW1400 EVM Trigger Input)

    all together (Please refer to AFE5809 User's Guide Page 12 Figure 10).

    These considerations are very important in order to capture the same data in parallel.

    Thank you!

  • 0 in reply to Chen Kung
    Prodigy 30 points

    Hi ,

    We are using kintex ultrascale device

    Test cases:

    We are operating in 16 bit mode and 10MHz, 25.6MHz and 40 MHz sampling frequencies, currently we are not using decimation in this test case

    when using toggle pattern,  we are not getting proper data( bit shift is happening) , in all other test patterns the data is coming fine.

    When we are using Analog input mode, the sine wave is coming proper, but when are comparing phase difference across the channels it is not as expected.

    Can u help us regarding this, or can u provide us any reference code so that we can directly use in xilinx FPGA devices.?

  • 0 in reply to charan teja
    TI__Genius 12025 points

    Hi,

    We will look into your question more details.

    also for your question,

    please refer to: 


    You can download the FPGA code from the following link: www.ti.com/.../slwc115

    Thank you!

  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi,

    when you are using Analog input mode,

    from device to another device, you need to provide all the devices with synced external clock-in

    (please see AFE5809 datasheet page 95 figure 109)

    the sine wave is coming properly.

    This is very important.

    Thank you!

  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi,

    Please be careful and notice the following:

    Please let us know below:

    Thank you!

    you may need to apply a TRIG signal on the TRIG_TX pin. 

     for example,

    If they enable the decimation, the first thing is to look if SYNC word 2727 comes out at the same time.

     

    Also how much phase difference they are talking about?