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Original question:

ADC122S021: Extra tracking pulse before data readout

ADC122S021: coninuously read out ADC (ADC122S021) with permanent CS LOW

Thomas Donner
Prodigy 130 points
Part Number: ADC122S021

Hi

We already use the this ADC and read out the data continuously with an FPGA. At the moment we generate 32 Clock cycles with CS=LOW and 2 extra cycles with CS = HIGH.
I´m not sure if it is possible/allowed by the datasheet to hold the nCS permanently low and read permanently alternating the both chanels.

If yes, is it also possible the fix grounding the nCS pin?


Kind Regards

Thomas

  • 0
    TI__Mastermind 24940 points

    Hello,

    yes this device is capable of doing that. With CS low, the SDI can change the next channel to be sampled. 

    But I would not suggest tying CS low permanently. Having CS available, will allow you to fix any clocking miscounts, or mismatch between SDI and clock

    It is good practice to bring CS high once conversions needed are complete

    Regards

    Cynthia