ADC122S021: Extra tracking pulse before data readout

Hello,

It seems that the attachment did not go through correctly. Would you please try again using the icons/selection tools provided through the text box.

You have confirmed that timing, PCB layout, and software haves all remained the same from previous build to this build?

I am not sure what you mean by "tracking pulse" but from your comment it sounds to be an extra pulse appears in the DOUT data?

please include a scope shot of the extra pulse in the attachments

Regards

Cynthia

Hi Cynthia

Thanks for your reply. I will try to do the attachment once more, -æ now both as PDF and PPT.

Yes, it is same software and same PCB version. I have searched for other wrong/failing components, but without luck.

Neither I cannot see, which of these should be able to make this fail, then the signals and their integrity seem OK.

According to the datasheet the first 3 clk cycles (after CS) are the tracking mode (SCLK is low by CS-start and therfore directly into trackmode).

MSB is clocked out on the 4th clock, as shown in the top figure of the attacment, which is what I will consider as the correct case. 

However, in the "cold case" (room temperature) the MSB is first present on the 5th clock, which gives an offset in the reading of the frame. 

Hope this made the issue more clear.

/CarstenADC_fail.pptx0310.ADC122S021_fail.pdf

Thanks Carsten,

The scope shots are very helpful. It does look like the SDO is shifted over one clock pulse.

Let's start by eliminating the new boards/set up

Can you remove the failing device from the new boards to a board from an older build that had not shown any failures? If the fail follows the device then we have eliminated the new build.

After that, we can start debugging it.

It seems that this is only affecting the first conversion after CS falling edge. From the scope shot, the second conversion result seemed correct. Is this correct? I would like to use an input at max positive scale. This will clearly show when the SDO line is outputting zeros and valid SDO data.

I have some general questions. How many devices are failing? Does temperature have a big effect? For example, do you see it at colder temperatures, and does it get worse?

Regards

Cynthia

ADCs_read_OK.pdfADCs_read_fail.pdfIsolator_difference.pdf

Hi Cynthia

As suggested I tried to exchange the ADC between two failing- and two OK-boards. The fail follow the boards. You can see how the readings are affected on attached plot. Then I tried to derive more information from the timing and saw a difference in the CE signal falltime (app 2us=working, 5us=bad). Then I tried to exchange the driver (opto-isolator) and that made the OK board bad and vice versa. So that must be the root course. Now I need to figure out why the CTR apparently has gone so low for this device, but for that I cannot blame the ADCs. However, in the ADC spec there is no limit for the CE-falltime, but only to the "deadtime" surrounding this. Is it correct? Anyway, thanks for the effort you have put into this case.

/Carsten