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ADS4449EVM: Values of Delays

Danilo A.
Mastermind 25645 points
Part Number: ADS4449EVM
Other Parts Discussed in Thread: ADS4449

Hi Team,

We've received a request from a customer for the following values of delays of ADS4449.

what is maximum delay between clkoutabp and clkoutabn?
does this delay remain stable?
does the delay shift over the time?
After which time does the delay shift?

The 4 questions apply for :
- delay between clkoutabp/clkoutabm and dab[13:0]p/dab[13:0]n
- delay between dab[13:0]p and dab[13:0]n
- delay between clkoutcdp/clkoutcdm and dcd[13:0]p/dcd[13:0]n
- delay between dcd[13:0]p and dcd[13:0]n

Do we have this information?

Regards,

Danilo

  • 0
    TI__Mastermind 18095 points

    Danilo: Please see below.  --RJH

    what is maximum delay between clkoutabp and clkoutabn?
    does this delay remain stable?
    does the delay shift over the time?
    After which time does the delay shift?

    The clkoutabp/n is a differential output clock referenced to the LVDS data output.  There is no data or expected delay between positive (p) and negative (n) side nor any variation over time.

    Delay between clock output and data pins are specified in the setup and hold times in section 6.7.  Setup time is 850 ps and hold time in 840 ps.  The timing diagram shown in Figure 40.

    --RJH

  • 0 in reply to RJ Hopper
    TI__Guru* 91947 points

    Danilo,

    Attached is info regarding additional timing values from the design team.

    Regards,

    JimTiming info.docx

  • 0 in reply to jim s
    TI__Mastermind 25645 points

    Hi Jim,

    The customer has follow up questions below.

    " Digital Channels AB and CD are sampled by a FPGA. Have you any ideas to guarantee that AB sample n and CD sample n will be sampled at the same time?

    I know I can make the ads4449 generate a pattern. But I want this pattern to be generated at exactly the same time with delay lower then 0.5ns. Even less if

    possible. Until now the pattern is generated as soon as I write it in the pattern generator. Which gives me delays between patterns generated on the different

    channels"

    Regards,

    Danilo

  • 0 in reply to Danilo A.
    TI__Guru* 91947 points

    Danilo,

    All four channels have asynchronous test pattern generators. This cannot be done.

    Regards,

    Jim