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ADC32RF45: Alignment of data from ADC

Part Number: ADC32RF45


Hai sir

We want to align the data from ADC32RF45, we are using channel 1 with four lanes 

LMFS is 8224 and Bypass with 14 bit Resolution

In the first frame 2 octets are coming like   A[13:6], A[5:0], 00

we want to align all four lanes data in one frame to retrieve RF input signal properly.

Please suggest us about alignment of all four lanes output from ADC32RF45.

Thank you
Roja Veereddy

  • Hi Roja Veereddy,

    As shown in Table 15 in the datasheet, first sample (A0) is sent on first lane (DA0), second sample (A1) is sent on second lane (DA0) and so on for next samples A and A3.

    Regards,

    Vijay

  • Hai sir

    The output of the ADC32RF45 is in 2's complement format and we are getting output with 32 bit from transceivers, how can we frame all lane samples to retrieve original input. 

    can we change the 2's complement format to signed or directly we can do.

    Can we take directly 16 bit or only input A samples we need to take.

    Please suggest us how the framing can be happend.

    Thanks

    Roja Veereddy.

  • Hi Roja Veereddy,

    If you get 32 bit data from each JESD lane, then each of this 32 bit data has two ADC samples. These two samples from each of four lanes need to be interleaved to get 8 continuous samples (with data from all four lanes). Within the 32 bits from first lane, first 16 bits contain sample A0 next 16 bits contain sample A5. Similarly, second lane 32 bit data contains sample A1 in first 16 bits and A5 and so on.

    From each 16-bit sample data, last two bits can be dropped to get 14-bit sample. You have to convert each sample from 2's complement format to signed.

    Regards,

    Vijay

  • Hai sir

    Thank you for this reply.

    16 bit has to convert from 2's complement to signed or 14 bit format has to convert from 2's complement to signed.

    Please give us idea to get ouput.

    Thanks

    Roja Veereddy

  • Hi Roja Veereddy,

    First remove the zeros at the end then covert 14 bit data from 2's complement to signed.

    Regards,

    Vijay

  • Hai sir

    Need to remove 00 from the MSB of the 16 bit right 

    please clarify this

    Thanks

    Roja Veereddy

  • Hai sir

    We tried the framing as per you said, but it didn't get.

    We tried test pattern signal i.e. 12 bit RAMP, we got first sample is on [31:16] A0 and 5th sample is on [15:0]A0.

    The following image shows the digital block of ADC32RF45, we did according to this. we got ramp signal but framing is like

    1st sample is on Lane 0 is [31:16] A0

    5th sample is on Lane 0 is [15:0] A0

    2nd sample is on Lane 1 is [31:0] A1  and so on

    Please help us to retrive the signal 

    Please find the image 

    Thanks

    Roja Veereddy

  • Hi Roja Veereddy,

    As clearly indicated in the format '00' is in last two LSB. Please remove those.

    I think you mean to say you get (before removing two zeros at the end):

    1st sample is on Lane 0 is [31:16] A0

    5th sample is on Lane 0 is [15:0] A5

    2nd sample is on Lane 1 is [31:16] A1

    and so on.

    It should be:

    1st sample is on Lane 0 is  [15:0]  A0

    5th sample is on Lane 0 is [31:16] A5

    2nd sample is on Lane 1 is [15:0]  A1

    and so on.

    I think it's just a inversion in the way 32 bits are shown in the FPGA (which 16 bits are shown first). Irrespective of that, interpret the samples order alignment based on ramp increment and retrieve the signal. 

    Regards,

    Vijay