This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1241: Noise and fmod artefacts on Inputs

Part Number: ADS1241
Other Parts Discussed in Thread: ADS124S08, ADS1240

Dear Gentlemen,

We are using ADS1241 for almost 5 years know and we realized a strange behavior with our board. The follwing parameter are used:

1. Quarz 4,9151MHz, no starting problems

2. speed-Bit = 0

conclusion: fmod = 38,4Hz

What we can measure now during ADC is doing a measurement  is a noise floor on the ADC inputs with a certain frequency of 153,6kHz which is related to 4* fmod. How is this possible and what can we do against is? Our measurement-values we need from the ADC are "dancing" correlated to the noise on the ADC-inputs. Are there certain PCB-Layout hints especially to this ADC (I cound not find any)?

We need help as soon as possible.

Kind regards

Christian

  • Hello,

    here are oszi-prints from the fmod disturbances.

    about 153,6kHz disturbances on Pin 16 (AIN7) (38,4Hz*4).

    yellow: nDRDY-Pin: falling edge = new data in output-register. First date is thrown away, because of maybe wrong date from previous data-conversion. Disturbances are present during second conversion.

    So what to do?

    Kind regards

    Christian

  • Hi Christian,

    Can you help provide a little more background on this issue? You say you have been using the ADS1241 for 5 years and have not had this problem before, and just recently it has started? Or has this problem existed during your entire development time? If the problem is new, has anything changed in your design, layout, etc. that could cause such a disturbance? It is rather odd for something like this to just "show up" after years of testing.

    Do you have an anti-aliasing filter on the inputs of your ADC? If so, what are the component values? It might be helpful to send a schematic if you can.

    Here are some general grounding and layout best practices for precision ADCs: https://e2e.ti.com/support/data-converters/f/73/t/755516

    -Bryan

  • Hello Brain,

    I did not develop this board, but I am now investigating measurement errors, which occur to our temperature measurement with PT100 (resistance based calculation). What we noticed is that one basic voltage measurement to calculate the resistance of the PT100 is fluctuating, I I did measure disturbances, as shown above on all ADC-Inputs. The uncertain temperature measurement was never addressed by customers before, but in the end of last year. I really do not know, if the problem exists since the board was developed.  

    We do differential measurements with two inputs. Any input has a 1kOhm resistance coupled to 10nF to the other input. The 10nF are shown in the ADS1241MEVM pdf on page 8 (schematic: C2, C5; R3, R4, R5, R6 are 1kOhm at our design).

    Regards Christian

  • Excuse me Bryan, for writing "Brain".

  • Hi Christian,

    I would try modifying the values of the input filters to see if that makes a difference. With the current implementation you have I am not sure you are going to get very good fMOD rejection (anti-aliasing). Please see this link for more details: https://e2e.ti.com/support/data-converters/f/73/t/955466?tisearch=e2e-sitesearch&keymatch=faq%3Atrue

    Fortunately the ADS1241 does not sample very quickly so you should be able to reduce the 3dB BW of the filter considerably before it starts impacting the overall measurement settling time. I would also include the common-mode filters (for example C1 and C3 in the ADS1241EVM schematic) in your design.

    Please give this a try and let me know what the results are. I would also point out that we have newer generations of this ADC available, specifically the ADS124S08. This device has better performance, more features, lower noise, lower power, smaller size, and lower cost. I recognize it will not be possible to change out the ADC in this current PCB, but I would strongly consider it for future revisions or new projects.

    -Bryan

  • Hi Christian,

    Can you send me your configuration settings? Specifically if you have the buffer enabled? This could certainly cause issues if your input is looking into the relatively low impedance input structure of the ADS1241 with buffer disabled.

    You might also specifically consider reducing the size of the input resistors and increasing the size of the differential capacitor, per my previous comment about changing the filter BW.

    This app note explains some of these suggestions in more detail: https://www.ti.com/lit/an/sbaa090/sbaa090.pdf

    -Bryan

  • Hello Brain,

    Thank you very much for the last link with sbaa090.pdf. On page 6 there is described which clocks are used for the first integrator stage in relation to PGA. So we use PGA = 16 within one measurement so we know now what voltages are "fluctuating". Within this measurement we use the internal buffer (BUFEN = 1). The input signals are in the range between 50mV...60mV. I already tried to introduce certain caps from the inputs to ground as common mode filters. They are sufficient,  but first we do not want to change the circuit and the layout. Is there something possible to change software to reduce the disturbances?

    Thanks Christian

  • Excuse me Bryan, for writing "Brain" again....sorry...my fault.

  • No worries about the name Christian, it happens all the time :)

    If you cannot change the hardware portion, the only option left would be to implement some sort of post-filtering in your MCU. If the noise is occurring at a specific frequency e.g. 150kHz, then you could potentially implement a digital bandstop filter to remove this frequency. I don't have more to offer on this specific topic since we are focused on ADC related questions, but I would guess there is generic code out there that you could modify for your specific MCU.

    -Bryan

  • Bryan, I have to come back to you regarding the artifacts,

    I noticed, that we have switched off the input buffer(s) within this certain measurement. We do sequentially two other measurements with switched on buffer(s) before that certain measurement, and during these two measurements I can not see any artifacts from the sampling frequency of the first integrator. So  the artifact have something to do either the buffer is switched on (no artifacts) or not (artifacts are present).

    And this is the main difference between  these two options and now I have a question related to the buffers. In the datasheet can be read the following:

    "INPUT BUFFER The input impedance of the ADS1240/41 without the buffer enabled is approximately 5MΩ/PGA. For systems requiring very high input impedance, the ADS1240/41 provides a chopper-stabilized differential FET-input voltage buffer. When activated, the buffer raises the ADS1240/41 input impedance to approximately 5GΩ.The buffer’s input range is approximately 50mV to AVDD–1.5V. The buffer’s linearity will degrade beyond this range.Differential signals should be adjusted so that both signals are within the buffer’s input range."

    We have signals per Pin which are in the range from 50mV...60mV. The differential voltage is then much more smaller.  The text from the datasheet is at this point not clear enough, because the buffers are also explained in https://www.ti.com/lit/an/sbaa090/sbaa090.pdf and there on page 7 are buffers shown per pin. This confuses me. The question is: do we have to use the buffer or not?

  • Hi Christian,

    I am a bit confused now. Before you said:

    "So we use PGA = 16 within one measurement so we know now what voltages are "fluctuating". Within this measurement we use the internal buffer (BUFEN = 1)"

    I took this to mean you have the buffers on, and when you have the buffers on you are seeing the artifacts. However, in your last post you said:

    "So  the artifact have something to do either the buffer is switched on (no artifacts) or not (artifacts are present)"

    So this statement seems to conflict with the first statement. Can you clarify?

    You are going to see some voltage drop on the 1kohm input resistors due to the aforementioned input currents. The buffer separates the input pins from the modulator sampling circuitry so this effect is mitigated. Therefore, I would assume you want the buffers on at all times. As you correctly mentioned however, the buffer limits the absolute input voltages you can apply to the inputs so you need to respect this more limited input range. Otherwise the buffers start operating in their nonlinear region and the output data will be inaccurate.

    -Bryan

  • Hello Bryan,

    to clarify this: when the buffers are on, we do not have artifacts of the sampling of the first integrator, when the buffers are off, I see artifacts of the sampling of the first integrator.  We use PGA =16 and have without buffer switched on artifact of 153,6kHz, when PGA is set to 4 I measure 76,8kHz...so yes, the artifaces are coming from the first integrator stage.

    Did I understood correctly, that the artifacts are the voltage drop of the external 1kOhm during the cap of the first integrator is charged, when the buffer is switched off?

    Second: When the buffer is on on AIN6 and AIN7, and we do a differential measurement  do we have to consider, that the input voltages of each input should be over 50mV or should the differential voltage between AIN6 and AIN7  over 50mV to avoid non linearity of the buffer?

    Thanks again

    Christian

  • Hi Christian,

    Thank you for clarifying.

    Yes, given the information at hand, I would assume the sampling currents are being drawn across those input resistors when the buffer is disabled. You might see the magnitude of the error reduce if you also reduced the size of the input filter resistors. I believe I mentioned that you should reduce the size of the input filter resistors in a previous post (and increase the size of the differential filter cap).

    The reduced input range due to the buffer is relative to the absolute voltage on each pin. So the voltage on each pin (AIN0-AIN7 & AINCOM) must be 50 mV above AGND and 1.5 V below AVDD. These voltages are relative to AGND. The differential voltage (in your case, AIN6 - AIN7) is referred to in the ADS1241 datasheet as the "full-scale input voltage range", and is +/-VREF / gain when RANGE = 0

    So, applying 50mV to AIN6 has 0% margin on the absolute input voltage, which might cause errors if the supplies, input signal, etc. drift. But, applying 50mV between AIN6 and AIN7 is certainly fine, as long as the absolute voltage on each pin meets the datasheet requirements.

    -Bryan