• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 419 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS54J60: Signal acquired with half the amplitude of the input signal

Omelio Barba Leal
Prodigy 10 points
Part Number: ADS54J60

Hi, TI

We are using ADS54J60 with the following configuration parameters (see attached image):

  1. DDC block configuration: Decimate-by-4 with IQ Outputs.
  2. Sampling Rate: 320 MSPS.
  3. Mixer frequency (Fixed at Sampling Rate/4): 80 MHz.
  4. Register 44h of Main Digital Page (6800h): DIGITAL GAIN = 0h.

We are injecting a 70MHz tone into the analog input of the ADCs and when we plot the acquired data we successfully obtain a 10MHz but with half the amplitude of the 70MHz tone. RF generator output is matched to 50 Ohm.

We believe that the reason may be given by the fact that quadrature demodulation causes the amplitude at the output of each component to be divided by 2.

Could you please clarify whether or not the DDC block compensates for this loss of amplitude or do we need to compensate manually writing some value on DIGITAL GAIN field of register 44h in the Main Digital Page. We could not find this information in the datasheet (SBAS706D).

If the DDC block, by default, already compensates for this amplitude loss, could you give us some advice about what could be happening?

Best regards,

  • 0
    TI__Guru* 91947 points

    User,

    You should not be seeing a divide by 2 amplitude in the output. Verify you have the proper input on both analog input pins. Make sure to issue a hard reset after the clocks are provided to the ADC. Attached is a config file I used with this setup and see no issues.

    Regards,

    Jim

    ADS54J60_4x_dec_Fs_4_IQ_4421.cfg

  • 0
    Prodigy 10 points

    Hi, Jim

    Thanks for your answer.

    Looking at the “ADS54J60_4x_dec_Fs_4_IQ_4421.cfg” configuration file that you attached we could see that you are effectively adding a digital gain of 6dB, that is, you are multiplying x2 the amplitude of the acquired signal. This is observed in line 9 of the file.

    Omelio Barba Leal said:
    Could you please clarify whether or not the DDC block compensates for this loss of amplitude or do we need to compensate manually writing some value on DIGITAL GAIN field of register 44h in the Main Digital Page.

    It is clear then that the DDC block does not automatically compensate for the 6dB loss (half the amplitude) of quadrature demodulator, it is necessary to compensate it manually by writing the Digital Gain register (0x680044).

    However, the following concern arises, if the digital gain is applied before the DDC block then we would be limiting the dynamic range of the input signal. On the other hand, if the digital gain is located after the DDC block, the dynamic range of the input signal would not be affected.

    Could you please tell us if the DIGITAL GAIN is applied before or after the DDC block. According to the block diagrams of datasheet (see attached images) it seems to be located before the DDC.

    Thank you in advance,

  • 0 in reply to Omelio Barba Leal
    TI__Guru* 91947 points

    User,

    The digital gain is applied after DDC to compensate the conversion loss with complex decimation. There is no reduction in the dynamic range on the front end.

    Regards,

    Jim 

  • +1 in reply to jim s
    Prodigy 10 points

    Thanks,

    Regards,