DAC38RF82EVM: Not getting expected FPGA clock frequency from DAC38RF82EVM with DCLK Divider =1 (FPGA clock and SYSREF).

Imran Sheikh31

Hi,

We are unable to get FPGA clock frequency (250MHz) from DAC38RF82EVM with DCLK Divider=1 (FPGA Clock and SYSREF). We are able to get the expected FPGA clock frequency (125/83.33/62.5/50MHz) for other DCLK Divider values (2/3/4/5).

DAC38RF82EVM is configured in CMODE3.

1.Jumper JP10 is open (Enable On-Chip PLL Clock Mode).

2.Provided a 4dBm external reference clock=250MHz to SMA J4.

3.Checked the PLL Enable box and enter the desired on-chip PLL reference clock frequency.

please check the attached PPT for more details.

Thanks,

Imran

Issue with DCLK divider=1 for CLKout0 and 1.pptx

over 5 years ago

+1 Kang Hsia over 5 years ago

TI__Guru* 82995 points

Hi Imran,

in the DCLK source pull-down, try select either the Bypass mode or Divider + DCC + HS setting to see if you can observe the 250MHz clock.

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DAC38RF82EVM: Not getting expected FPGA clock frequency from DAC38RF82EVM with DCLK Divider =1 (FPGA clock and SYSREF).