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ADS807: ADS807E CLK interference analog input Pin24/25

Part Number: ADS807

Hello:


I USE ADS807E A/D converter. when FPGA out a clock to ADS807E,This clock superposition on analog input signal, as below,THANKS

Hopewu

2020.5.29

  • Shimei,

    The clock rising and falling edges from the FPGA may be to fast for this older ADC and causing noise to get on the analog input. Clock jitter may also be the issue.  The data going to the FPGA could be the problem. Please see the two sections called "Clock Input Requirements" and Data Outputs" of the data sheet on page 14. You may be able to slow down the clock edges with settings inside FPGA or add a series dampening resistor (around 22 Ohms) on the clock trace if possible. If you can add the resistor, place the part as close as possible to the source.

    Adding series dampening resistors or a buffer to the output data may also be required if there are long traces between the two parts.

    Regards,

    Jim