ADS1191: DC Lead-off detection issues

For AC Lead-off detection, is the measuring of the excitation signal(1/4 sample rate) done on the ADS1191 and the status bit reflects the result? It is not clear from the data sheet if it is done on chip or requires post processing off the chip.

Thanks,

Jim

Hi Jim,

The AC Lead-off detection requires post-processing using the data capture at the output. The AC Lead-off section (pg 49) in the datasheet explains the how the AC Lead-Off is accomplished. 

Thanks.

-TC

Thanks TC for your quick reply. Yes page 49 is what I referred to, then the lead-off status register is only for DC Lead-off detection? AC Lead-off detection needs additional processing with the ADS1191 output data, this may not be suitable for low power application where additional processing consumes more power.

Does TI have a recommended DC coupled input circuit with RLD DC bias? Maybe some modifications to the one Ryan recommended in my first post so it can be used with DC Lead-off detection.

Thanks,

Jim 

Hi Jim,

The lead-off status register (LOFF_STATP, LOFF_STATN) is only used with DC Lead-off detection configuration. These two registers are set by the on-chip lead-off comparators which can be powered down if dc lead-off is not used.

You can refer to Figure 94 & 96 of the ADS1298 datasheet for DC couple scheme with RLD bias. You will need to have anti-aliasing filter to prevent any undesired aliasing effects.

I listed a few posts on the DC-couple configuration with anti-aliasing filter. I hope you find them useful.

https://e2e.ti.com/support/data-converters/f/73/t/942143?ADS1294-Space-constrained-PCB-antialiasing-filter-for-low-frequency-input

https://e2e.ti.com/support/data-converters/f/73/t/160037?Anti-Aliasing-Filter-for-Delta-Sigma-Converters

https://e2e.ti.com/support/data-converters/f/73/t/146993#533945

Thanks.

-TC

Hi TC,

Thank you for the confirmation and the linked information.

Looking through the ADS1298 data sheet, figure 94 is for a separate RLD electrode scheme. Combining Figure 95 and 96 (see below) appeared to be what Ryan Andrews suggested approach in my 1st post, RLD used for DC bias and R2/C2 as anti-aliasing.

What made the Ryan's suggested circuit AC coupling input was the C1 (Cblock in Figure 95). Is there any issue or concern if C1 is bypassed as below? 

I did a quick test with that by short out C1 and was able to capture the signal although the DC was not near 0 as before but it stayed at a constant voltage so the signal was OK just with a larger offset. In fact the wave form was somewhat better due the R1C1 high pass filter was gone now so that the lower frequency passed through.

Please let me know your thoughts on this.

Thanks,

Jim