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Original question:

DLP3021LEQ1EVM: What is the external adapter DEF060A for in the DLP3021LEQ1EVM demo board?

DLP3021LEQ1EVM: Debugging FPGA in Code Composer on DLP3021LEQ1EVM demo board.

Vladimir Zhukov
Intellectual 370 points
Part Number: DLP3021LEQ1EVM
Other Parts Discussed in Thread: MSP430G2553-Q1, DLP3021-Q1, DLPC120-Q1

Hello!

How to view signals on pins of Xilinx chip in DLP3021LEQ1EVM demo board via Code Composer?
Does SPI programmer make FPGA debug?

Yours faithfully Zhukov Vladimir.

  • 0
    TI__Mastermind 27780 points

    Hi Zhukov,

    The SPI programmer does not support FPGA debugging. FPGA debugging and monitoring is not enabled on the DLP3021LEQ1EVM for customers. The SPI interface only supports FPGA register read/write commands using DLP Control Program, and flash programming of the NOR flash memory using DLP Composer. Code Composer Studio only supports debugging and flash programming of the MSP430G2553-Q1 microcontroller on the DLP3021LEQ1EVM.

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Hi Akeem,

    Thanks for the answer.

    Can you clarify, if you use the XILINX programmer, will it be possible to track signals on the FPGA pin?
    Do you only need Code Composer or XILINX's Vivado development tool?

    Does the JTAG demo board have a XILINX connector?

    Yours faithfully Zhukov Vladimir.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27780 points

    Zhukov,

    It is best to view the FPGA as a DMD controller, similar to the DLPC120-Q1. The FPGA is intended to be a black box controller exclusively designed for the DLP3021-Q1 that users have no visibility into, no ability to customize the code of, and no debug capabilities, so it does not support any Xilinx programmer or JTAG tools.

    The source code for the FPGA DMD controller is TI proprietary, so I am unable to share this with you, just as if it were the DLPC120-Q1.

    Code Composer Studio has nothing to the with the FPGA development or internal code. The MSP430 MCU is optional, so Code Composer Studio becomes optional, and only serves as a external host controller that formats input data (from a PC or other serial source) into SPI commands to the FPGA. The MSP430 is a redundancy to the FTID-to-SPI cable connection between the PC and EVM.

    Based on your previous posts, you are trying to project 2D black and white patterns, which the DGP EVM can support as-is. For what reason do you need to access the FPGA signals?

  • 0 in reply to Akeem Whitehead
    Intellectual 370 points

    Akeem,

    Based on your previous posts, you are trying to project 2D black and white patterns, which the DGP EVM can support as-is. For what reason do you need to access the FPGA signals?

    I am planning to change the code in FPGA to use DMD in black and white only. I want to send a 2D image and set up mirrors in one clock cycle. And not to depend on three bars for an RGB color image.
    And I have a desire to reconfigure the tri-color RGB format to black and white mode without grayscale.
    I am now choosing a system on a demo board that will allow this to be done.
    Since I don't have much programming experience. I count on support from Texas Instruments.

    Yours faithfully Zhukov Vladimir.

  • 0 in reply to Vladimir Zhukov
    TI__Mastermind 27780 points

    Zhukov,

    It appears you will need to swap out the RGB-LEDs to a single white-LED to support your method of generating the black-and-white content if you do not intend on using RGB color mixing to create the black-and-white content. We do have plans for a new version of the DGP EVM to be released next year that will have a white-LED option available.

    DLP Composer uses the red channel for single LED output (e.g. map red channel to the white LED), which requires you to change the sequence duty cycles to R=100, G=0, B=0 in Composer, and then change your image format to “grayscale” on the Image/Video tab in Composer (monochromatic).

    The DLP3021-Q1 has a refresh rate of 25Hz, so this is how fast you can switch between different image patterns.