DLP2021-Q1: DLP2021 - Setup time and Hold meet , but Rise time and fall time not meeting

Hi all,

This is pursues a former email discussion. The maximum rise and fall time at the DLP2021-Q1 inputs is 2.5 ns. Customer have measured 7.3 ns on SCTRL which is the worst offender, and all other DLP input signals are also above 2.5 ns. Setup and hold times are met despite this.

This is most likely to the high capacitive load on the outputs of the 74AVC8T245  level shifter.

Could this be an issue for the DLP2021 device?

Best regards,
François.

Hi Francois,

Is the root cause confirmed to be the 74AVC8T245 level shifter by comparing the rise/fall time of the input to the output? If so, are they able to use a different level shifter with a faster rise/fall time to mitigate this risk?

I assume the customer's setup-and-hold time validation where the up to 7.3ns rise/fall time has been observed was performed at room temperature. Has the customer performed any system level testing across temperature (-40 to 105 C) to determine if the rise/fall time becomes worse and results in image artifacts? As is the case with any situation performing outside of the datasheet spec limits, DLP cannot confirm whether a >2.5ns rise/fall time is guaranteed to behave as expected since we have not tested this condition ourselves.

What is likely attributing to the rise/fall time margin of the AM263x based solution is that the SAC bus is operated at 50MHz instead of the nominal 76.2MHz.

Thank you, Akeem.

Srinath S, just to make sure, could you please check the rise and fall times at the inputs of the 74AVC8T245 level shifter? As per its specification, its slope should be less than 5 ns/V.

I assume that the above will be ok since the AM2632 MCU drives directly the level shifter. Then, we could try to get shorter transition edges at the 74AVC8T245 output by adding some pull-up resistors there. Try 10 kΩ on e.g. SCTRL since it is the worst offender, and see how much this decreases the transition time. You may go down to 1 kΩ, but it is better to keep the pull-up value high to minimize the extra current consumption.

As Akeem advised, we will also have to see what the transition times look like over temperature. But let's first see at room temperature.

Thank you.

Best regards,
François.

Hello Francois and Akeem.

Actually Level shifter input and output difference is around 0.3 ns.

Example input of level shifter has rise time of 3.5ns and output of level shifter have rise time around 3.8 ns.

Thanks for solution suggestions ,In this case we need to place resistors especially at input of level shifter.

If further, need improvement , we need to place these resistors at output of level shifter also  

Let us check the solution with 10 kΩ or 1 kΩ. and let know results .

Thanks and regards

Srinath

Hello Francois and Akeem,

Is it mandatory to meet this rise time and fall time for DLP2021 , despite meeting setup and hold time ?

If not meet rise time and fall time , what is the risk we are going to face here ?

Thanks and regards

Srinath

Hello Srinath,

Let me remind you Akeem's statement: "As is the case with any situation performing outside of the datasheet spec limits, DLP cannot confirm whether a >2.5ns rise/fall time is guaranteed to behave as expected since we have not tested this condition ourselves."

So, we should try to avoid violating the rise and fall time limits.

Have you experimented with pull-ups at the inputs and/or outputs of the level shifters? What was the outcome?

By the way, we are looking here at an interface that operates at a nominal 76.2 MHz. Have you simulated the path from AM2632-Q1 to SN74AVC8T245? What is the length of the traces of the signals between these two devices?

Best regards,
François.

Hello Francois Charlot ,

Yes we tested by adding pull-up resistors of 1Kohms and 10K ohms at input and Output of level shifters.

We didn't see any changes , its same rise time and fall time at input and output of level shifters.

Thanks and regards,

Srinath.

Hello Srinath,

Thank you. We have asked some support from the SN74AVCT8T245BQ1 application team who have a few inquiries:

1. Could you please disconnect all SN74AVCT8T245BQ1 outputs and measure their rise and fall times? Please post here the full list of tr/tf with the normal loads and after having disconnected everything.
2. Can you confirm that the only load that you have between the Sitara AM2632 MCU and SN74AVCT8T245BQ1 is the PCB tracks and nothing else? Please report here the tr/tf times that you have measured on the SN74AVCT8T245BQ1 inputs.
3. You said that the rise time of the SN74AVCT8T245BQ1 outputs vary from 3.8 to 7.3 ns. Besides they drive different DLP2021 signals, what's different between these signals? Trace length, trace width, PCB layer(s), number of vias traversed... 

Thank you.

Best regards,
François.

Changing status to "waiting for customer".

Hello Francois,

Thank you for debug suggestions,

There is only PCB tracks in-between  Sitara AM2632 MCU and SN74AVCT8T245BQ1 .

All signals are length matched.

But, Currently we are in final sample which is Design freeze state.

We don't have further layout sample as per customer.

We like to understand that will it be issue for not meeting rise time and fall time , even after meeting Setup and hold time.

Thanks and regards

Srinath

Hello Srinath,

As already stated, "As is the case with any situation performing outside of the datasheet spec limits, DLP cannot confirm whether a >2.5ns rise/fall time is guaranteed to behave as expected since we have not tested this condition ourselves."

We should pursue the investigations along the lines of my Aug 7th post above. Please give details answers and measurements. Thank you.

Best regards,
François.