• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 624 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DLPLCRC964EVM: FPGA selection & programming

Kieran N
Prodigy 20 points
Part Number: DLPLCRC964EVM
Other Parts Discussed in Thread: DLP991U, DLPC964, , DLPLCR99EVM

Tool/software:

Hi again team,

Context: I'm currently looking at designing a system aiming to minimise feature size of a lightfield at 395-405 nm. See here for more info. I've currently arrived on the DLP991U DMD in order to minimise mirror pitch whilst remaining in the UV spectrum. That has lead me to the DLPLCR99EVM/DLPLCRC964EVM combo, which seems acceptable for 405nm.

Question: The DLPC964 documentation leads me to understand that an external FPGA is required. Can this be avoided (and data loaded directly from a PC) if high-speed applications aren't being utilised? I'm happy to have only one pattern available, with a reboot & config adjustment required to change patterns, if that simplifies hardware/dev.

If one is required, the documentation recommends a AMD Virtex 7 FPGA VC707, which has been discontinued, leading me to the AMD Virtex 7 FPGA VC709. I'm not experienced with programming FPGAs/using Vivado, is this simply a matter of loading the VHDL code provided, modifying patterns via the BPG pattern txt files, and selecting via the TI-provided GUI? 

Thanks again in advance,

  • +1
    TI__Intellectual 1930 points

    Good afternoon , 

    An external FPGA is optional and is not needed in order for the DLPLCRC964EVM to communicate and display patterns to the DLPLCR99EVM. 

    The DLPLCRC964EVM can be assembled in either of two ways:

    1. The standalone system (DLPLCRC964EVM and DLPLCR99EVM)
    2. The standalone system with an attached front-end device (VC-707 or another external front-end device) to the DLPLCRC964EVM HPC FMC connectors J1 and J2

    You could use either approach to send patterns from the DLPLCRC964EVM to the DLPLCR99EVM for display. More information regarding assembly instructions can be found in the DLPLCRC964EVM Users Guide, along with an overview of the hardware and software features of the DLPLCRC964EVM system. Additionally, the user's guide explains how to display and run test patterns from the DLPC964 GUI to the standalone system and any external front-end device connected to the DLPLCRC964EVM. 

    Unfortunately, the VC-707 has been discontinued from Xilinx, but our team is working on an alternative solution that should be available for our customers in 1H25. We have already determined that we are going to be using the AMD Virtex UltraScale+ FPGA VCU118 as the alternative external front-end device, and we have been recommending this solution to other individuals as well that want to develop systems with a front-end device. The VCU118 is backwards compatible to the VC-707 making it easier to integrate with the DLPLCRC964EVM. The VHDL code that is provided on the DLPLCRC964EVM Product page is targeted for the VC-707, so those files will not work for another external device. 

    Hopefully this helps!

    Regards,

    Tristan Bottone

  • 0 in reply to Tristan Bottone
    Prodigy 20 points

    Perfect, thanks again for your help Tristan.

    One (hopefully final) follow up question: do you know what pattern rate and input data bandwidth the DLPLCRC964EVM can operate at without the use of an FPGA? I definitely won't need one for my experimentation, but it would be helpful to try understand whether I will need to purchase one down the line.

    Appreciate the help.

  • 0
    TI__Intellectual 1930 points

    I am happy to help, .

    The maximum 1-bit pattern rate for the DLPLCRC964EVM is 12,390 Hz.

    When there is no external front-end device attached to the DLPLCRC964EVM, each data lane can achieve up to 3.6 Gbps, utilizing 32 high-speed serial data lanes from the DLPLCRC964EVM (output) to the DLPLCR99EVM (input). However, with the addition of an external front-end device, each data lane can achieve up to 10 Gbps, with 12 high-speed serial data lanes going from the external front-end device (output) to the DLPLCRC964EVM (input).

    If any other questions arise, do not hesitate to reach out again via the E2E forums!

    Regards,

    Tristan Bottone