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Original question:

DLPLCRC964EVM: FPGA selection & programming

DLPLCRC964EVM: FPGA Board Selection and patterning rate

Greg Dachtler
Prodigy 10 points
Part Number: DLPLCRC964EVM
Other Parts Discussed in Thread: DLP991U, , DLPLCR99EVM, DLPC964, DLP991UUV

Tool/software:

Similarly to this linked thread, I'm trying to design a system using the DLPLCRC964EVM driving the DLPLCR99EVM with the DLP991U DMD. I see that the data rate is increased when an external FPGA board is used, but I want to confirm that to reach the full 12kHz+ patterning rate that the DLP991U is capable of I would need the front-end FPGA board. Also, in the linked thread, it was mentioned that the recommended AMD 707 FPGA was discontinued, and that a new solution would be provided based on the AMD Virtex UltraScale+ FPGA VCU118 in the first half of 2025. Has that been completed and is there a new VHDL code package that can be used?

Thank you!

  • 0
    TI__Intellectual 1750 points

    Hello Greg, 

    Yes, that is correct - the DLP991U is capable of reaching 1-bit pattern rates up to the full 12kHz pattern rate when a front-end device is connected. 

    Additionally, we will not be moving forward in utilizing the VCU118 as the new front-end device for the DLPLCRC964EVM + DLPLCR99EVM. Instead, we've decided to transition to the AMD Zynq UltraScale+ MPSoC ZCU102 EVM kit. This decision was mainly based on the closer alignment between the FMC signals offered between the VC-707 and ZCU102. The VC-707 and ZCU102 have the same FMC pinout (VCU118 had a different FMC layout with additional I/O), so our team moved forward with the ZCU102 since this serves as a more direct plug-in replacement to the now discontinued VC-707. The updated solution is currently under development and is expected to be available in 2H25. We appreciate your patience and apologize for the delay.

    As of now, here are a few options we can recommend:

    • You can obtain a ZCU102 EVM Board from AMD and use the Applications FPGA Source files we have for the VC-707 as a reference to build what you would need for your system with your own FPGA development effort
    • We can provide contact information to our third-party developers like Visitech, Vialux, and InVision, where you can work with them to either develop the Applications FPGA or purchase a system of what you would need

    Please note that once this is released, the ZCU102-based design will not provide customers with a data input interface to the DLPC964 but will function solely as a test pattern generator.

    Thank you and Best Regards, 

    Tristan Bottone

  • 0 in reply to Tristan Bottone
    Prodigy 10 points

    Thank you for the information, Tristan! I look forward to seeing the updated solution when it comes out. Can you expand on what you mean by your last note that the new design won't have a data input interface to the controller but only generate test patterns?

  • 0 in reply to Greg Dachtler
    TI__Intellectual 1750 points

    Greg, 

    Of course! As for the last note, I am happy to clarify more, please see below.  

    The ZCU102-based solution will be designed to operate as a standalone test pattern generator for the DLPC964, meaning it won't accept or process any external user image data. Instead, the design will support internal pattern generation (e.g., Checkerboard, ramps, etc.), including both built-in test patterns and user-defined custom pattern sequences that can be preloaded into the FPGA (This will have the same behavior that was seen on the VC-707). 

    Although the ZCU102 won't provide a data input interface to the DLPC964, users will still be able to configure and run custom sequences that are embedded into the bitstream or stored in associated memory. So, while it won't allow customers to dynamically stream new images into the DLPC964, it does allow customers to define and store their set of custom patterns. This makes it suitable for system development and evaluation where dynamic streaming is not required. 

    Best Regards,

    Tristan Bottone

  • 0 in reply to Tristan Bottone
    Prodigy 10 points

    Hi Tristan,

    Apologies for the delay. Thank you for clarifying the behavior of the ZCU102. I believe I will need the capability to stream images into the DLPC964 at the full 12kHz rate for my research application. Is the limitation on data streaming because of the ZCU102 hardware or the VHDL code package (i.e., could I develop my own package for the ZCU102 that would allow for streaming, or would I need to select a different FPGA for that)?

    In a separate but related question, would it be possible to get CAD models of the DLPLCRC964EVM and the DLPLCR99EVM?

    Thank you!

    Greg Dachtler

  • 0 in reply to Greg Dachtler
    TI__Intellectual 1750 points

    Hey Greg, 

    No worries and of course!

    The limitation on data streaming in the current ZCU102-based application isn't due to the ZCU102 hardware itself, but rather the current VHDL code package and system design. The ZCU102-based solution is intended to operate in a "pre-loaded pattern mode" where the patterns are stored in the FPGA memory or sent as pre-configured bitplanes, and does not have dynamic streaming.  The ZCU102 is capable of supporting this type of architecture, but it would require custom development. Achieving full streaming would require significant modification to the FPGA design to implement the necessary data pipeline and timing requirements required. 

    As for the DLPLCRC964EVM and DLPLCR99EVM CAD models, please review the information below.

    The DLPR115 & DLPR116 design files include the Bill of Materials (BOM), schematic, and assembly files for the related EVM. The DLPM074 Mechanical CAD file is the 3D-CAD model for the DLP991U/DLP991UUV DMD which includes the .STP file for the DMD.

    Best Regards, 

    Tristan Bottone