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TMS320C5505: Confirm the usage of FLUSHIFIFO

Kaka
Guru 24520 points

Part Number: TMS320C5505

Hi TI Experts,

Please let me confirm the following question.

[Question]
When customer used the Double packet buffer on DPB bit, would you please show me the way to flash/clear the both buffer by using the FLUSHFIFO?

Best regards.

Kaka

  • 0
    TI__Guru 65405 points
    Hi Kaka,

    I've forwarded this to the c55x experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Mastermind 30365 points
    Hi Kaka-san,
    I will need to check on the response to your questions with a C5000 USB expert who is currently out of office. Please give a few days. Thanks for your patience.

    In the meantime I assume you are referring to the USB_flushFifo function at C:\ti\c55_lp\c55_csl_3.07\inc\csl_usbAux.h wich does a TX and RX FIFO flush?

    Lali
  • 0 in reply to Lalindra Jayatilleke
    Guru 24520 points
    Hi Lali,

    Yes, they have already checked this function but they did not use that CSL function which you mentioned because it seems that it does not take care for the double packet buffer.

    Best regards.
    kaka
  • 0
    TI__Guru 56245 points

    Hi Kaka-san,

    According to the TRM for C5505:

    If the FIFONOTEMPTY bit is 1 after the first set to the FLUSHFIFO bit.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Guru 24520 points
    Hi Ming,

    I could not understand about your answer.
    Would you please explain your answer in detail?

    [My question]
    >When customer used the Double packet buffer on DPB bit, would you please show me the way to flash/clear the both buffers by using the FLUSHFIFO?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru 56245 points

    Hi Kaka-san,

    Sorry. my snap shot from the C5515 TRM got removed by the E2E. According to the C5515 TRM:

    Also if there are any data packets in the FIFO, indicated by the FIFONOTEMPTY bit (bit 1 of PERI_TXCSR) being set, they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).

    NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled.

    So the steps are:

    1. if  FIFONOTEMPTY is 1 then set FLUSHFIFO to 1

    2. check FIFONOTEMPTY  again, if it is 1 then set FLUSHFIFO to 1 second time.

    3. if FIFONOTEMPTY is 0, then you are done

     

    Best regards,

     

    Ming

     

  • 0 in reply to Ming Wei
    Guru 24520 points
    Hi Ming,

    Thank you for your explanation.
    Please let me confirm the following question.
    According to the TRM, the FLUSHFIFO bit is described as below.
    "Note: FlushFIFO has no effect unless the TXPKTRDY bit is set. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO."
    So, it seems that the TXPKTRDY bit need to set as manual before use the FLUSHFIFO. Should customer follow this explain?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru 56245 points

    Hi Kaka-san,

    The TXPKTRDY bit need to set to 1 manually when the data is copied into the FIFO to mark the data is ready to be transmitted. It will be cleared when the data is sent out.

    There is no need to manually set the  TXPKTRDY bit to 1 before  use the FLUSHFIFO.

    Set the TXPKTRDY bit to 1 without copy data into the FIFO will result a zero length packet transmit. See my answer to the other question from you for details.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Guru 24520 points
    HI Ming,

    Thank you for your response. I could understand about the TXPKTRDY.
    By the way, please let me confirm the FLUSHNOTEMPTY bit.
    According to the TRM, this bit was described as follow.
    "This bit is set when there is at least 1 packet in the Tx FIFO. You should clear this bit."
    Would you please teach me the mean of "You should clear this bit."?
    Does it mean that user need to clear this bit in manual?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru 56245 points

    Hi Kaka-san,

    I think you meant "FIFONOTEMPTY" bit.

    According to the TRM, the FIFONOTEMPTY is cleared by set FIFOFLUSH bit to 1 one or two times.

    Also if there are any data packets in the FIFO, indicated by the FIFONOTEMPTY bit (bit 1 of

    PERI_TXCSR) being set, they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).

    Best regards,

     

    Ming