Hi TI Experts,
Please let me confirm the following question.
[Question]
When customer used the Double packet buffer on DPB bit, would you please show me the way to flash/clear the both buffer by using the FLUSHFIFO?
Best regards.
Kaka
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Hi TI Experts,
Please let me confirm the following question.
[Question]
When customer used the Double packet buffer on DPB bit, would you please show me the way to flash/clear the both buffer by using the FLUSHFIFO?
Best regards.
Kaka
Hi Kaka-san,
Sorry. my snap shot from the C5515 TRM got removed by the E2E. According to the C5515 TRM:
Also if there are any data packets in the FIFO, indicated by the FIFONOTEMPTY bit (bit 1 of PERI_TXCSR) being set, they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).
NOTE: It may be necessary to set this bit twice in succession if double buffering is enabled.
So the steps are:
1. if FIFONOTEMPTY is 1 then set FLUSHFIFO to 1
2. check FIFONOTEMPTY again, if it is 1 then set FLUSHFIFO to 1 second time.
3. if FIFONOTEMPTY is 0, then you are done
Best regards,
Ming
Hi Kaka-san,
The TXPKTRDY bit need to set to 1 manually when the data is copied into the FIFO to mark the data is ready to be transmitted. It will be cleared when the data is sent out.
There is no need to manually set the TXPKTRDY bit to 1 before use the FLUSHFIFO.
Set the TXPKTRDY bit to 1 without copy data into the FIFO will result a zero length packet transmit. See my answer to the other question from you for details.
Best regards,
Ming
Hi Kaka-san,
I think you meant "FIFONOTEMPTY" bit.
According to the TRM, the FIFONOTEMPTY is cleared by set FIFOFLUSH bit to 1 one or two times.
Also if there are any data packets in the FIFO, indicated by the FIFONOTEMPTY bit (bit 1 of
PERI_TXCSR) being set, they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).
Best regards,
Ming