• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 100 subscribers
  • Views 614 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Core-DDR3 Performance on C6678

Mnr Bht
Prodigy 40 points
Other Parts Discussed in Thread: TMS320C6678

I try to read data from DDR3 (512 MBytes) by 1 core of a TMS320C6678, the testbench conditions are as follow :

 - L1D Cache=32K ; L1P Cache=32K

 - L2 Cache=256K

 - Read buffer=512 MBytes

 - Consecutive reads from the buffer to the bancs level (core level)

=> Performance of about 2 GBytes Per Second

I found it very small, comparing it to L1 for example (about 17 GBytes/s)

Am I doing something wrong ? or is it normal ?

Thanks

  • 0
    Prodigy 40 points

    More info about my problem :

    In the configuration code line, that i added :

    CACHE_enableCaching(CACHE_CE00);

    The constant CACHE_CE00 is not defined for the compiler even if the CSL library is included .. how to make it work ?

    Is DDR3 extern memory cacheable by default ?

    Another problem I experience is that when I try to access DDR3 from another core than the core0, it seems that the cache doesn't work !!

    Thanks

  • 0
    Genius 3770 points

    Hi,

    First, you can have a look at this thread for the theoretic memory performance of the main data path in C6678:http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/135086.aspx

    Second, I think the actual performance of DDR3 will be a discount of the theoretic one, because the DDR3 has its own access latency and you cannot achieve 100% rate of bandwidth. So I use EDMA to test the probable performance of DDR3, when read data from DDR3 to MSMC RAM, it can achieve 6~7 GBbyte/s, which is 60%~70% of theoretic figure(10664MB/s). Just for you reference.

    Allen

  • 0 in reply to Mnr Bht
    Genius 3770 points

    As for the cacheability of DDR3, the default is non-cacheable, which is denoted in Table 4-22 of CorePac User guide.

    You can use CACHE_enableCaching to enable the region, but the parameter to this API is not CACHE_CExx, it should be (uint8 mar). For DDR3, mar is started from 128.

    Make the proper configuration as above and see the situation of another core. Hope it helps.

     

    Allen