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About C6678 DDR address space

g.f.
Guru 15520 points

Hi,

I have a question about C6678 DDR3.

If we want to use 8GByte DDR3 memory, how to configure in the C6678?
In the the C6678 datasheet, it seem that we can use up to 8GByte DDR3.
But in page.27 Table 2-2, there is only 2GB address space for DDR3 EMIF data.

I understand as follow, but I don't know it's either correct or not.

* Need to configrure XMC MPAX Segment Registers of MSMC and
  for example if using 2 segment and setting each SEGSZ to 4GB,
  we could use up-to 8GB. Am I correct?

  So, to use 8GByte need to configure more than 2 segment.
  Am I correct?

best regards,
g.f.

  • 0
    Guru 10750 points

    Hi G.F,

    Yes, the internal DSP is 32bit so as you mentioned you can use the XMC to translate the logical address space (32bit) to physical address space (36bit) but at a given time you are using 32bit address space,

    Thanks,

    HR

  • 0 in reply to HRi
    TI__Mastermind 23525 points

    Correct.  Maybe attached diagram helps visualize...

  • 0 in reply to tscheck
    Guru 15520 points

    Hi HR and tscheck,

    Thank you for the reply.

    I understood that MPAX will translates logical memory(32bit) into physical memory(36bit).
    But I'm confused about accessing to DDR3 from each 8 cores.

    DDR3 data space starts from 0x8000_0000 to 0xFFFF_FFFF(2GB),
    so I guess that maximum external addressable external memory from each core is 2GB.
    How to program the code for accessing upper 6GB area?

    By the way in C6678 datasheet page.27 Table 2-2,
    Physical 36-bit Address range of DDR3 EMIF data is 0x8_0000_0000 to 0x8_7FFF_FFFF.
    and noted as follow:
    ==============================================================================
    The memory map only shows the default MPAX configuration of DDR3 memory space.
    ==============================================================================

    So, can I think that physical address range for DDR3 is
    from 0x8_0000_0000 to 0x9_FFFF_FFFF(8GB)?

    best regards,
    g.f.

  • 0 in reply to g.f.
    Guru 10750 points

    Hi G.F,

    As you are the system development you should know how each of the internal 32bit address converts to the 36bit physical address (programing the MPAX), you don't need to do anything with your SW you need just to program the MPAX, please note that each core have his own MPAX registers so each core can convert differently his internal 32bit to the external 36 bits,

    Hope this helps,

    HR

  • 0 in reply to HRi
    Intellectual 820 points

    Hi,HRi:

    Why designer design that each core has his own MPAX regissters?

  • 0 in reply to Armstrong
    Guru 10750 points

    Hi Armstrong,

    This gives the ability to define/split the global memory usage for each core (so for example you can define 1G of memory for each core with no overlapping), there could be of course overlap between the defined memories cross the cores,

    Thanks,

    HR

  • 0 in reply to HRi
    TI__Mastermind 23525 points

    Another use case for MPAX is control cache-ability of MSMC memory.  By default, MSMC memory is cached in L1, but you can disable this by remapping MSMC to a non-cachable address range.  Or, you can map MSMC memory to look like an L3 memory that is cached in L2.  Please see:  http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/147532.aspx for details.  Having MPAX per core allows you do have all this control per core, in addition to the discussion from HRi regarding separate DDR spaces per core.

    Regards,

    Travis

  • 0 in reply to tscheck
    Guru 15520 points

    Hi HR and tscheck,

    Thank you so much.
    I'm sorry for taking your time.

    Now, I understood.

    best regards,
    g.f.

  • 0 in reply to tscheck
    Guru 15520 points

    Hi HR and tscheck,

    Sorry, I have one more thing to be sure.

    I want to know the physical address range for DDR3.
    Is it from 0x8_0000_0000 to 0x9_FFFF_FFFF(8GB)?

    best regards,
    g.f.

  • 0 in reply to g.f.
    TI__Expert 6815 points

    You are right, that is the full 8GB address range for DDR3.

    We only publish the default 2GB physical range in the data manual. The user is expected to extend the address range beyond default using the MPAX.

  • 0 in reply to Aditya
    Guru 15520 points

    Hi Aditya,

    Thank you for the reply.

    I understood.

    best regards,
    g.f.