C66x CorePac MAR registers configuration

Daisuke Maeda

Guru 20205 points

How does Bit[2] in the MAR registers be treated?

The CACHE_setMemRegionInfo() in CSL can set PCX bit which is Bit[2] in the MAR registers, but the CorePac user's guide does not describe PCX bit.

How does PCX bit be controlled? Must PCX bit and PC bit be consistent?

This topic is discussed here: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/166571.aspx

Best regards,

Daisuke

over 11 years ago

0 Chad Courtney over 11 years ago

TI__Mastermind 30825 points

The PCX bit is for enabling/disabling an external memory (from CorePac perspective) as a cache. For example MSMC is an external shared memory. If has cache capability (potential future devices - non currently available support this) then this would be used to enable the cache. On C6678 which the topic refers to, the device is a Keystone I device and the MSMC does not support a cache mode.

Best Regards,

Chad

0 Daisuke Maeda over 11 years ago in reply to Chad Courtney

Guru 20205 points

Hi Chad,

Thank you for your reply.

Best regards,

Daisuke

0 Daisuke Maeda over 11 years ago in reply to Chad Courtney

Guru 20205 points

Hi Chad,

Is there the description of MSMC cache mode in the documents of Keystone II devices?
I cannot find it. Our customer requires us to show it.

Best regards,

Daisuke

0 Chad Courtney over 11 years ago in reply to Daisuke Maeda

TI__Mastermind 30825 points

Daisuke,

I apologize, I should have said future devices. None of the current Keystone II devices have a MSMC or external memory that supports a cache mode. This is why the bit-field was initially marked as reserved and still is marked as reserved in most documentation.

Best Regards,

Chad

0 Daisuke Maeda over 11 years ago in reply to Chad Courtney

Guru 20205 points

Hi Chad,

Thank you for your reply.

Best regards,

Daisuke

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C66x CorePac MAR registers configuration