problems about C6678 core0 initialization

Hi Jie wang,

It is a simple procedure as far as I know.

We will provide you the instructions step by step.

1. Hardware details:

Connect the power cord and usb cable between the target board ( You will find two emulators in shannon EVM; one is XDS560V2 and onborad emulator; connect it to XDS560V2. IF you are connecting to XDS560V, make sure the RED LED and Yellow LED glows after connected.)

2. Create a target configuration file, *.cxml and select the following options.

Connection --> Blackhawk XDS560V2- USB trace emulator.

Board or device type --> TMS320C6678

Click on "Advance " in *.cxml file and click Core 0---> provide the gel file path : "..\..\..\..\mcsdk_2_01_02_06\tools\program_evm\gel\evmc6678l.gel"

click Test connection --- Observe the results like below.

3. Right click the *.ccxml file ---> launch the selected configuration.

4. In the CCS debug window., Right click on Core0 and click "Connect Target" ; This will run the gel file and initialise the DDR and do other intitializations.On succeeful target connections, you should get the console messages like below from the GEL file.

Regards,

Shankari

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Hi Shankari,

Thanks  for your reply!

I did following your step, but because of the connecting errors I didn't provide the gel file path for core0.Instead, after connecting core0,I right click on the target and choose "Open the GEL Files View ",then I choose "Load GEL ..".Finally,I choose "Scripts"->"EVMC6678L Init Fuctions"->"Global_Init_Setup".

Here is the result,and you can get more details in the word file I upload including  running on the normal board.

And when we use our application to initialize the interface(SPI/DDR) instead of the gel file,the error dialog pop-up.

And the errors only happened on the core0,we can successfully initialize the interface(SPI/DDR) on other cores.

Can you tell me why?Is it possible the chip is bad?

Eagerly awaiting your reply !

7633.gel_run.docx

Hi Jie,

You have to provide the appropriate gel file.

Click on "Advance " in *.cxml file and click Core 0---> provide the gel file path : "..\..\..\..\mcsdk_2_01_02_06\tools\program_evm\gel\evmc6678l.gel"

What is the gel file you have provided?? post the screenshot of the *.ccxml in CCS .

Regards,
Shankari

Hi,

I have reviewed the attached doc file, it seems that your DDR fails on test or the initialization failure.

2. core0 runs the gel on the normal board,though the parameters are not entirely match with the chip

C66xx_0: GEL Output: Setup_Memory_Map...

C66xx_0: GEL Output: Setup_Memory_Map... Done.

C66xx_0: GEL Output: C6678L GEL file Ver is 2.004

C66xx_0: GEL Output: Global Default Setup...

C66xx_0: GEL Output: Setup Cache...

C66xx_0: GEL Output: L1P = 32K  

C66xx_0: GEL Output: L1D = 32K  

C66xx_0: GEL Output: L2 = ALL SRAM  

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: Main PLL (PLL1) Setup ...

C66xx_0: GEL Output: PLL in Bypass ...

C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains...

C66xx_0: GEL Output: Security Accelerator disabled!

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

C66xx_0: GEL Output: PA PLL (PLL3) Setup ...

C66xx_0: GEL Output: PA PLL Setup... Done.

C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...

C66xx_0: GEL Output: DDR3 PLL Setup... Done.

C66xx_0: GEL Output: DDR begin (1333 auto)

C66xx_0: GEL Output: XMC Setup ... Done

C66xx_0: GEL Output:

DDR3 initialization is complete.

C66xx_0: GEL Output: DDR done

C66xx_0: GEL Output: DDR3 memory test... Started

C66xx_0: GEL Output: DDR3 memory test... Failed

C66xx_0: GEL Output: Main PLL (PLL1) Setup ...

C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.

C66xx_0: GEL Output:            SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.

C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

And the errors only happened on the core0,we can successfully initialize the interface(SPI/DDR) on other cores.

Can you tell me why?Is it possible the chip is bad?

How are you initializing the interfaces from other cores? The gel file init the interfaces only from core0. Are you modifying the gel file to do the same? Please check the gel file code snippet below init only on core0 (Global_Default_Setup_Silent()).

// Only core 0 can set these
if (DNUM == 0)
{
for (count = 0; count < PLL_REINIT_MAX_COUNT; count++) {
// Setup Pll1 DSP @ TARGET_FREQ
status = Init_PLL(PLL1_M, PLL1_D);

if (status == -1) {
GEL_TextOut( "Error in Setting up main PLL, please power cycle the board and re-run Global Default Setup...\n" );
while (1);
}

if (!count) {

// Setup all Power Domains on
Set_Psc_All_On( );
}
// Setup Pll3 pass clk @ 1050 MHz
Init_Pll3(PLLM_PASS, PLLD_PASS);

// Setup Pll2 DDR3 PLL @ 667 MHz
Init_Pll2(PLLM_DDR, PLLD_DDR);

GEL_TextOut( "DDR begin (1333 auto)\n");
xmc_setup();
ddr3_setup_auto_lvl_1333(0);
GEL_TextOut( "DDR done\n");

if(ddr3_memory_test() == 0) {
break;
}

}

if (count == PLL_REINIT_MAX_COUNT) {
GEL_TextOut( "PLL and DDR Initialization failed ...\n");
} else {
GEL_TextOut( "PLL and DDR Initialization completed(%d) ...\n",,,,, count);
}

// Configure SGMII SERDES
configSGMIISerdes();

GEL_TextOut( "Enabling EDC ...\n");
EnableEDC_OneforAll();
GEL_TextOut( "Enabling EDC ...Done \n");

GEL_TextOut( "Configuring CPSW ...\n");
setCpSwConfig(); 
GEL_TextOut( "Configuring CPSW ...Done \n"); 
}

Hi,

Have you selected same parts as EVM or different parts DDR, Flash etc? What is the DDR used in your custom project?

Have you done the DDR leveling for the selected DDR? Please check the EVM documents, Schematics and BOM etc from below link and confirm.

Thank you.

Hi Raja and Shankari G,

Thanks for your reply !

We modify the parameters about DDR and provide the gel path for core0 according to your advices.And we find the result of initialization on the other custom board is successful but the errors still happen on the abnormal board.By the way,the types of DDR and FLASH are same between the two board.

The errors:

We find the error happend when the gel writes the memory of DDR initialization registers.Why?

We check the PLL intialization registers and find different values in address 0x023100e4 between the successful board and the error board.We find the register in the PLL User's Guide .

What is it mean the RESET bit and POR bit?Is it related with the errors cannot write the DDR initialization registers?

Eagerly awating your reply !

Got the DDR  memory test passed after your modification? If Yes, please share complete console messages as above.

C66xx_0: GEL Output: DDR3 memory test... Failed

Thank you.

What is the difference between abnormal and normal board?
In my understanding, both are not working (abnormal).

As per your log 1) It fails to write DDR registers.
As per your log 2) It succeed with init and fails on DDR memory testing.

Please attach the gel file used for connecting with core here for review.

Thank you.
Regards,
Rajasekaran K

Hi Rajasekaran K:

Firstly ,thanks for your replies!

I have onced mentioned that I modified the gel file and provided path to core0 on our normal and abnormal board.I also canceled the  "DNUM" limitation,so the "Global default init setup " can run on any core.

Here is the complete message .

1.we provide the gel path for core0 on normal board and core1 on abnormal board,the console is same.

2.we provide the path for core0 on abnormal board,the errors what is can not write the registers happend when gel configuring DDR refresh rate.And if we delete the configuring refresh rate code,the same errors(cannot write the register) happend when running the next code.

 

We have checked our board design and nothing found.Why the error happend?

The "c6678l_dzs.gel file is my modified one .And   ""gel_console.docx " is the complete message we got from gel initialization.

Eagerly awating your reply!

Regards,

Jie.

c6678l_dzs.gel

gel_console.docx

 

Hi Jie,
I have requested our hardware experts to look into the issue. Thank you for your patience.

Hi Jie,

Based on the results that you are seeing it appears that you do not have a stable DDR3 interface. This can be caused by a number of factors on the board. Some of these factors include the stability of the power supply, jitter on the DDR reference clock or DDR3 layout issues. It could also be caused by a problem with configuration. Since that is the easiest to fix, lets look at that possibility first.

Can you provide the RegCalc and PhyCalc spreadsheets that you modified for your design. Can you provide the length matching information for the layout of your board? You mentioned that you are using the same memory parts as the EVM could you provide exact part numbers you have on your board? Can you provide some details on your board such as the number of layers, the stackup and the layers used for routing the DDR3 interface. 

You also talk about a normal board and an abnormal board. What is the difference between these two boards?

Regards,

Bill

Jie,

We also need some clarification.  Some of the posts appear to be basic connection and emulation issues.  Are you able to run the Out of Box Demo on the EVM?  Are you able to connect to the C6678 on the EVM using CCS?  Are you able to run the GEL and then access the DDR3 memory on the EVM?  We need to know that you can successfully do these things.

Tom