Boot core 1 using core 0, C6657

Dear all,

In addition to the previous post , I have adjusted the code in order the second to write in DDR3 but seems that the second core never wakes up. Moreover the register KICK have not the values that I write in order to unlock them. It is any other action in order to have access in these registrs? These registers  are not editable in memory browser window as well

Please find the code below

/*
 *  ======== main.c ========
 */

#include <xdc/std.h>

#include <string.h>
#include "platform.h"

#define DEF_INIT_CONFIG_PLL1_PLLM  		0
#define DEF_INT_MEM_TEST_CORE_ID   		1
#define MAGIC_ADDR     					0x8ffffc
#define DEVICE_REG32_W(x,y)   		  *(volatile uint32_t *)(x)=(y)
#define DEVICE_REG32_R(x)    		   (*(volatile uint32_t *)(x))
#define BOOT_MAGIC_ADDR(x)  		   (MAGIC_ADDR + (1<<28) + (x<<24))
#define STATUS_ADDR					   (MAGIC_ADDR  - 0x4)


#define CHIP_LEVEL_REG  0x02620000
#define KICK0           (CHIP_LEVEL_REG + 0x0038)
#define KICK1           (CHIP_LEVEL_REG + 0x003C)
#define IPCGR(x)            (0x02620240 + x*4)

#define BOOT_MAGIC_NUMBER   0xBABEFACE

extern uint32_t platform_get_coreid(void);

typedef struct test_config {
    uint8_t print_info;
    uint8_t print_current_core_id;
    uint8_t print_switch_state;
    uint32_t init_config_pll1_pllm;
    uint32_t int_mem_test_core_id;
} test_config;

volatile int *status_bl = ( int * ) STATUS_ADDR;
/*
 *  ======== main ========
 */

void
write_boot_magic_number
(
    void
)
{
    DEVICE_REG32_W(MAGIC_ADDR, BOOT_MAGIC_NUMBER);
    int *ptr = (int *)0x80000000;
    while(1)
    {
        *ptr = *ptr +1;
    }
}

Int main()

{ 
    uint32_t coreId = platform_get_coreid();
    uint32_t core;
    platform_info pform_info;
    if(coreId == 0)
    {
        platform_init_flags  init_flags;
        platform_init_config init_config;
        test_config args;
        Platform_STATUS status;
        *status_bl = 54;
        /* Set default values */
        memset(&args, 0x01, sizeof(test_config));
        memset(&init_flags, 0x01, sizeof(platform_init_flags));

        args.init_config_pll1_pllm     = DEF_INIT_CONFIG_PLL1_PLLM;
        args.int_mem_test_core_id      = DEF_INT_MEM_TEST_CORE_ID;
        init_config.pllm               = args.init_config_pll1_pllm;
        if ((staatus = platform_init(&init_flags, &init_config)) != Platform_EOK) {
            //  aprintf("Platform failed to initialize, errno = 0x%x \n", platform_errno);
              return status;
        }
        platform_get_info(&pform_info);
        /* Unlock the chip registers */
        DEVICE_REG32_W(KICK0, 0x83e70b13);
        DEVICE_REG32_W(KICK1, 0x95a4f1e0);
        /* Writing the entry address to other cores */
        for (core = 1; core < pform_info.cpu.core_count; core++)
        {
            DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);

            /* Delay 1 sec */
            platform_delay(1);
        }
        for (core = 1; core < pform_info.cpu.core_count; core++)
        {
           /* IPC interrupt other cores */
           DEVICE_REG32_W(IPCGR(core), 1);
           platform_delay(1000);
        }
        //1
    }
    else
    {
       write_boot_magic_number();
   }
    while(1);
    return(0);
}

Hi,

Are you trying to load code to core 0 AND core 1? If that is the case, please check out our MAD utilities wiki. These utilities are designed for deploying code on multiple cores.

Other than the MAD utilities, we also recommend that if possible you combine the application image for the two core. Both the cores will execute the same application image in which control code is used to identify the core number  and execute code specific to a core. This has been demonstrated in the MCSDK example for SRIO boot which can be replicated on all boot modes. The default MCSDK SRIO example code is only work on SRIO boot mode only. For more information refer readme file on following path: \ti\mcsdk_2_01_02_06\tools\boot_loader\examples\srio\docs\

Here is the code you can do when you combine the application image:

coreNum = platform_get_coreid();

if (coreNum == 0)

{

 //Code to be executed on primary secondary core.

}

else

{

// Code to execute on secondary core.

}

Hope this helps

Thanks,

Hello,

Thank you for the prompt reply. I want to load core 1 via core 0 as in example in bootloader mode using pcie or srio.

As I mentioned in the previous post  I have noticed that the KICK0 and KICK1 registers are not editable.

How can I do in this way?

Best regards

George

Hi,

The example code might be correct, KICK registers would return zero. Take a look at below similar threads:

Refer below similar thread for load core1 via core0:

Thanks,

Hello,


But using this example the core cannot start the core 1
Best regards
George

Hello,

Any update in this issue?

Were you able to boot core1 from core0?

Hello ,

By mistake  I put my answer in other post.

Unfortunately no.

The core 0 cannot wake up core 1. I follow the steps that are described in the previous post , but I do not the code for the uart.

In the magic address  the write_boot_magic_address function address has been written.

But I have erase the default bootloader in the evm board. I do not know if this an important factor.

Thank you in advance

George.

I have attached the code that I try to execute.

Please also find the target configuration

<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS2xx USB Onboard Emulator_0">
        <instance XML_version="1.2" desc="Texas Instruments XDS2xx USB Onboard Emulator_0" href="connections/TIXDS2XXUSB_onboard_Connection.xml" id="Texas Instruments XDS2xx USB Onboard Emulator_0" xml="TIXDS2XXUSB_onboard_Connection.xml" xmlpath="connections"/>
        <connection XML_version="1.2" id="Texas Instruments XDS2xx USB Onboard Emulator_0">
            <instance XML_version="1.2" href="drivers/tixds560icepick_d.xml" id="drivers" xml="tixds560icepick_d.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds560c66xx.xml" id="drivers" xml="tixds560c66xx.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds560cs_dap.xml" id="drivers" xml="tixds560cs_dap.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds560csstm.xml" id="drivers" xml="tixds560csstm.xml" xmlpath="drivers"/>
            <instance XML_version="1.2" href="drivers/tixds560etbcs.xml" id="drivers" xml="tixds560etbcs.xml" xmlpath="drivers"/>
            <platform XML_version="1.2" id="platform_0">
                <instance XML_version="1.2" desc="TMS320C6657_0" href="devices/C6657.xml" id="TMS320C6657_0" xml="C6657.xml" xmlpath="devices"/>
            <device HW_revision="1" XML_version="1.2" description="C66x core" id="TMS320C6657_0" partnum="TMS320C6657" simulation="no">
                    <router HW_revision="1.0" XML_version="1.2" description="ICEPick_D Router" id="IcePick_D_0" isa="ICEPICK_D">
                        <subpath id="subpath_0">
                            <cpu HW_revision="1.0" XML_version="1.2" description="C66xx CPU" deviceSim="false" id="C66xx_0" isa="TMS320C66xx">
                                <property Type="filepathfield" Value="..\..\My Documents\5008.evmc6657l.gel" id="GEL File"/>
                            <property Type="numericfield" Value="0x0" id="TraceDeviceId"/>
                            <property Type="choicelist" Value="0" id="Slave Processor"/>
                            </cpu>
                        </subpath>
                    <subpath id="subpath_1">
                            <cpu HW_revision="1.0" XML_version="1.2" description="C66xx CPU" deviceSim="false" id="C66xx_1" isa="TMS320c66xx">
                                <property Type="filepathfield" Value="" id="GEL File"/>
                                <property Type="choicelist" Value="1" id="Slave Processor"/>
                            <property Type="numericfield" Value="0x1" id="TraceDeviceId"/>
                            <property Type="choicelist" Value="0" id="bypass"/>
                            </cpu>
                        </subpath>
                    </router>
                </device>
            </platform>
        </connection>
    </configuration>
</configurations>
?

/******************************************************************************
 * Copyright (c) 2011 Texas Instruments Incorporated - <a href="www.ti.com">http:/.../a>
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated emac the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/

/**************************************************************************************
 * FILE PURPOSE: Boot Hello World Example
 **************************************************************************************
 * FILE NAME: boot_helloworld.c
 *
 * DESCRIPTION: A simple hello world example demonstrating boot.
 *
 ***************************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "platform_internal.h"
#include "platform.h"

#define DEVICE_REG32_W(x,y)   *(volatile uint32_t *)(x)=(y)
#define DEVICE_REG32_R(x)    (*(volatile uint32_t *)(x))

#define CHIP_LEVEL_REG  0x02620000
#define KICK0           (CHIP_LEVEL_REG + 0x0038)
#define KICK1           (CHIP_LEVEL_REG + 0x003C)

/* Magic address RBL is polling */
#ifdef _EVMC6657L_
#define MAGIC_ADDR          0x8ffffc
#endif

#ifdef _EVMC6678L_
#define MAGIC_ADDR          0x87fffc
#endif

#ifdef _EVMC6670L_
#define MAGIC_ADDR          0x8ffffc
#endif

#define BOOT_MAGIC_ADDR(x)  (MAGIC_ADDR + (1<<28) + (x<<24))
#define IPCGR(x)            (0x02620240 + x*4)

#define NUMBER_OF_CORES     2

#define BOOT_MAGIC_NUMBER   0xBABEFACE

#define BOOT_NUMBER0   0xAAAA5555
#define BOOT_NUMBER1   0x11111111
#define BOOT_NUMBER2   0x22222222
#define BOOT_NUMBER3   0x33333333

#define DDR_ADDR0       0x81000000
#define DDR_ADDR1       0x82000000
#define DDR_ADDR2       0x83000000
#define DDR_ADDR3       0x84000000



#define BOOT_UART_BAUDRATE         115200


uint32_t platform_get_coreid(void)
{
    return (CSL_chipReadDNUM());
}

Platform_STATUS platform_delay(uint32_t usecs)
{
    int32_t delayCount = (int32_t) usecs * 850000000;
    int32_t start_val  = (int32_t) CSL_chipReadTSCL();

    while (((int32_t)CSL_chipReadTSCL() - start_val) < delayCount);

    return Platform_EOK;
}

/* boot_helloworld version */
char version[] = "01.00.00.01";

/* OSAL functions for Platform Library */
uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
{
    return malloc(num_bytes);
}

void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes)
{
    /* Free up the memory */
    if (dataPtr)
    {
        free(dataPtr);
    }
}

void Osal_platformSpiCsEnter(void)
{
    return;
}

void Osal_platformSpiCsExit (void)
{
    return;
}

/******************************************************************************
 * Function:    write_uart
 ******************************************************************************/
void
write_uart
(
    char*      msg
)
{
    uint32_t i;
    uint32_t msg_len = strlen(msg);

    /* Write the message to the UART */
    for (i = 0; i < msg_len; i++)
    {
      //  platform_uart_write(msg[i]);
    }
}

void
write_boot_magic_number
(
    void
)
{
    uint32_t                coreNum;

    coreNum = platform_get_coreid();

    DEVICE_REG32_W(MAGIC_ADDR, BOOT_MAGIC_NUMBER);

    while(1);
}

/******************************************************************************
 * Function:    main
 ******************************************************************************/
void main ()
{
    char                    version_msg[] = "\r\n\r\nBoot Hello World Example Version ";
    char                    boot_msg[80];
    platform_info           pform_info;
    uint32_t                coreNum, core;

    /* Initialize UART */
    coreNum = platform_get_coreid();
    if (coreNum == 0)
    {
      //  platform_uart_init();
      //  platform_uart_set_baudrate(BOOT_UART_BAUDRATE);

        printf("%s%s\n\n", version_msg, version);

        /* Unlock the chip registers */
        DEVICE_REG32_W(KICK0, 0x83e70b13);
        DEVICE_REG32_W(KICK1, 0x95a4f1e0);

        /* Writing the entry address to other cores */
        for (core = 1; core < NUMBER_OF_CORES; core++)
        {
            sprintf(boot_msg, "\r\n\r\nBooting Hello World image on Core %d from Core 0 ...", core);
            printf("%s\n",boot_msg);

            DEVICE_REG32_W(BOOT_MAGIC_ADDR(core), (uint32_t)write_boot_magic_number);

            /* Delay 1 sec */
            platform_delay(1);
        }
        for (core = 1; core < NUMBER_OF_CORES; core++)
        {
            /* IPC interrupt other cores */
            DEVICE_REG32_W(IPCGR(core), 1);
            platform_delay(1000);
        }

    }
    else
    {
        write_boot_magic_number();
    }

    while(1);
}

Hi,

In the other thread , customer confirmed that it is working on C6657 EVM so I am thinking that you have missed on the setup or procedure.

Few more to check:

1. Have you enabled the _EVMC6657L_ macro for correct magic address before building the project?

2. Have you power cycled every time before running this project?

Thank you.

Hello

Regarding the first bullet , in the image that I attached the program has written in the correct address,

the address of the function that is executed by second core.

About second core could you please clarify what you mean "power cycle every time"

I have followed the instructions. I have connected in the first core , I ran the code and then  I paused the execution and I check the L2 memory of the second core.

How to check if the IPCGR  interrupt takes place?

Best regards

Hi,
Lets assume, you have connected core0 with gel file then the application (.out) file is loaded and run using emulator for first time(I am considering this as a cycle).

If you want to run same/different the application on core0, please switch off and on the EVM again.

Thank you.

Hello,
I have done this with no effect
Best regards
George

Hello,

Any update to this issue?

We have followed the instruction but we cannot wake up the second core.

Is any other change either in cfg file or in the debugger settings.

We use the xds2xx usb emulator

Best regards

George

The project which we have shared does not require any .cfg file.

I do not know what went wrong on your setup and I am unable to re-produce the issue reported.

Do you have another board to test the same?

Thank you.

Hello,
Regarding the post above. We found what was wrong.
we have put the const and the test in L2 instead of DDR. However If you put the const and text in the L2 of the first core, you should copy the const and text from the L20 to L21. In addition ,the _c_int00 should be in DDR.

Hi Giorgos tsoumplekas,

we have put the const and the test in L2 instead of DDR. However If you put the const and text in the L2 of the first core, you should copy the const and text from the L20 to L21. In addition ,the _c_int00 should be in DDR.

Thank you for the post however I did not understand the issue. BTW, what is L20 and L21? Can you please clarify?

Thank you.

Hello

The issue was that we have put the .text and .const in 0x00800000 and the second core could not start the  execution. We solved this problem copying the .const and .text data from the L2 of the core 0 (L20)to the L2 of core 1(L21)