HI Champs,
I'd like to know Keystone II DDR3 layout guidelines for discrete components below.
(1) How long is a maximum trace length for address, command, control, and clock from KeyStone II device to the first DDR3 component?
(2) How long is a maximum trace length for DQ, DQS, DQS#, and DM from KeyStone II device to the first DDR3 component?
Thank you in advance for your cooperation.
Best regards,
j-breeze