Interrupt mechanism from ARM to DSP

Hi Ran!

Thank you very much for the information, that looks exactly like what I need, I'll try this as soon as possible (before end of monday) and keep you posted!

Thanks again,

Thomas.

Hi!

I read and tried a lot of things during the week-end and I think I'm getting pretty close to my goal. However it's still not working completely and I'm running out of ideas on the 'why'. Besides, I have a few questions remaining regarding the global interrupt mechanism:

1. Based on Configuring interrupts on Keystone devices and this thread (and several others from this forum), I understand that the CSL module is used to configure the CIC, which is the chip interrupt controller and the HWI module is in charge of the INTC which is the DSP's own interrupt controller and the code snippets given are sufficiently explicit to use those modules.

What I can only assume however, is the fact that the IPCGR directly triggers an event (id 105 on the 66AK2H according to the manual) and not a system interrupt, meaning that setting the first bit of this register to '1' will directly trigger the interrupt on the INTC (HWI module). Is that correct?

If this is indeed true, the example provided by the above thread is not relevant since it's using the CSL module to catch the CSL_GEM_IPC_LOCAL interrupt. Moreover I've not been able to find the definition of this macro anywhere in the sdk nor have I been able to find a list of all system interrupts possible on the device.

Based on the above, the following code should catch the interrupt raised by the IPC register:

Hwi_Handle ipcgr_hwi;

Hwi_Params hwi_params;
Error_Block error_block;

Hwi_Params_init(&hwi_params);
Error_init(&error_block);

hwi_params.arg = 1;

// Set the event id of the peripheral assigned to this interrupt.
hwi_params.eventId = 105;

// Disable the interrupt for now.
hwi_params.enableInt = FALSE;

Are the above assumptions and code correct?

2. On the ARM side, as you suggested, I should be able to write the IPGRN register accordingly to trigger the event. Here's the code I use:

#define REG_BASE (0x02620000) // mmap requires offset to be aligned on a page frontier.
#define KICK0 (0x38)
#define KICK1 (0x3C)
#define IPCGR_BASE (0x240)
#define IPCGR(x) ((IPCGR_BASE + (x*4)))

#define PAGE_SIZE 4096

#define READ32_REG(x) (*((volatile uint32_t *)(x)))
#define WRITE32_REG(x, n) (*((volatile uint32_t *)(x)) = n)

int main(void) {

	int dev_mem_fd = -1;
	void *reg_base = (void *)-1;
	
	if ((dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
		perror("descriptor opening error:");
		return -1;
	}
	
	reg_base = mmap(0, PAGE_SIZE, PROT_WRITE | PROT_READ, MAP_SHARED, dev_mem_fd, (off_t)REG_BASE); 
	if(!reg_base || reg_base == MAP_FAILED) {
		perror("mmap failed:");
		return -1;
	}
	
	fprintf(stdout, "* Initial IPCGR(i) values:\n");
	for (uint8_t i = 0; i < 8; ++i) {
		fprintf(stdout, "  * %u 0x%x\n", i, READ32_REG(reg_base+IPCGR(i)));
	}
	
	// Send interrupt to DSPs:
	
	/* 1. Unlock the Bootcfg MMR (memory mapped registers) in which
	 * IPGR belongs. By default those registers are locked after boot time,
	 * to unlock them two specific registers must be set with very specific
	 * data :
	 * see section 8.2.3.4 66AK2H specification.
	 */
	WRITE32_REG(reg_base+KICK0, 0x83e70b13);
	WRITE32_REG(reg_base+KICK1, 0x95a4f1e0);
	
	/* 2. Send the interrupt. */
	for (uint8_t i = 0; i < 8; ++i) {
		WRITE32_REG(reg_base+IPCGR(i), 0x11); // HERE THE BIT SHOULD BE SET
	}
	// Commit changes to the mapped file.
	msync(reg_base, PAGE_SIZE, MS_SYNC);
	
	/* 3. Relock MMR registers by writting anything else than the previous
	 * sequences in the KICK0-1 registers.
	 */
	WRITE32_REG(reg_base+KICK0, 0x42);
	WRITE32_REG(reg_base+KICK1, 0x1337);

	fprintf(stdout, "* Final IPCGR(i) values:\n");
	for (uint8_t i = 0; i < 8; ++i) {
		fprintf(stdout, "  * %u 0x%x\n", i, READ32_REG(reg_base+IPCGR(i)));
	}
	
	munmap(reg_base, PAGE_SIZE);
}

The problem is that the above code will produce the following result:

* Initial IPCGR(i) values:
  * 0 0x0
  * 1 0x0
  * 2 0x0
  * 3 0x0
  * 4 0x0
  * 5 0x0
  * 6 0x0
  * 7 0x0
* Final IPCGR(i) values: // Should have been 0x11
  * 0 0x10
  * 1 0x10
  * 2 0x10
  * 3 0x10
  * 4 0x10
  * 5 0x10
  * 6 0x10
  * 7 0x10

Meaning that the one bit I want to set is not set. Moreover, the KICK0 and KICK1 registers don't seem to be written in the first place... Do you have any idea what I might be missing?

3. Is the IPC register used by modules system (such as the IPC one)? I know it's also used at boot time, which is why I had to mask the interrupt in the first place. If that's the case, how can one use the SRCN bits of the register on the DSP to know where/why the interrupt is coming from?

4. I've seen a lot of references to the GEM interrupt controller but I've not been able to find the definition of the GEM acronym.

Thank you,

Thomas.

Hi Ran!

Thank you very much for the answers, I think I have a good insight on the global mechanism by now. I'll try what you suggest to very if setting the IPCGR bit triggers an event or a system interrupt. In the latter, I will be using the CSL functions described in the "configuring Interrupts on Keystone devices" guide.

However, could you please clarify the following points:

1. Is the IPC register used by modules system (such as the IPC one)?

2. Do you have an idea why the IPCGR bit is not set by the ARM code I provided?

Thanks again!

Thomas.

Can you close the thread please