[SRIO] question about srioDevice_init() and few things to clarify

Hi,

I have an another question from srioDevice_init(). Of course, this function is defined by developer. But in the pdk, it is included in device_srio_loopback.c
(I don`t understand why pdk includes loopback configuration file. it is confused for me to configuration for board2board test) Anyway, in the code, there is serdes configuration during device_init():

srioDefSerdesSetup(hSrio,srioSerdesVAddr,srio_ref_clock_156p25Mhz,srio_lane_rate_5p000Gbps,1);

but under below, there is also code related on reference clock:

CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x21);

And register description for PRESCALAR_SRV_CLK(defined in SetLLMPortIPPrescalar) is described like this,

The default value of 31 is for an ip_clk frequency of 312.5 MHz.
For different frequencies of ip_clk, use the formula:
ip_clk_frequency (in MHz) /10 rounded to the nearest integer.

So in my opinion, this example contains contradiction. Because serdes configuration is based on 156.25MHz, but LLM clock is based on 312.5MHz. In my case, I used 156.25MHz so I used like this:

CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x10);

Am I misunderstand something? If yes, please clarify this.

And ss I metioned before, I`m trying to test SRIO path in board2board (K2H <-> Xilinx FPGA). If DSP sends NWRITE(or NREAD) packet to FPGA, it can check in FPGA side(using chip scope). But in views of DSP, How can I check the packet sending from FPGA to DSP? It can check the data sending from FPGA to DSP in FPGA side. But data write in specific address(or read) doesn`t happened in DSP side(even if memory browser is operated periodically)

Thanks in advance.

Best Regards,

Chanseok.