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the definition for the duty of DDR[x]_CLK for AM3874

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Hi,

I would like to know the definition of the duty of DDR3_CLK that is output from AM3874 DDR controller.

I could not find its definition of DDR3_CLK duty on datasheet of AM3874. Is the definition based of JEDEC standard of DDR3?

Please let me know.

I appreciate your quick reply.

 

Best regards,

Michi

  • 0
    TI__Guru**** 170625 points

    Hi Michi,

    Michi Yama said:
    I would like to know the definition of the duty of DDR3_CLK

    Could you please provide more details? What do you mean by "the duty of DDR3_CLK"? Is it "duty cycle" or something else? Is it something mentioned in the JEDEC documentation?

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Guru 10030 points

    Dear Pavel-san,

    Thank you for your reply.

    As to your question, Yes, I am asking duty cycle of DDR3_CLK.

    I attached with JEDEC document of DDR3. JEDEC specify CLK period, high pulse width, low pulse width and so on.

    Please see it.

    0636.JESD79-3E.pdf

  • 0
    TI__Guru**** 170625 points

    Michi,

    Michi Yama said:
    I could not find its definition of DDR3_CLK duty on datasheet of AM3874.

    I also can not find the duty cycle of the DDR3_CLK in the AM387x datasheet. I can only find the DDR3_CLK cycle time tc(DDR_CLK), see section 8.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing.

    Michi Yama said:
    Is the definition based of JEDEC standard of DDR3?

    Yes, I think so. AM387x device supports JEDEC standard compliant LPDDR, DDR2 and DDR3 SDRAM devices with the features outlined in the DDR section of the datasheet. The section “Compatible JEDEC DDR3 Devices” shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

    8.13 DDR2/DDR3 Memory Controller

    The device has a dedicated interface to DDR3 and DDR2 SDRAM. The device dedicated interface also supports JEDEC standard compliant DDR2 and DDR3 SDRAM devices with the following features:
    • 16-bit or 32-bit data path to external SDRAM memory
    • Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices
    • Support for two independent chip selects, with their corresponding register sets, and independent page tracking
    • Two interfaces with associated DDR2/DDR3 PHYs
    • Dynamic memory manager allows for interleaving of data between the two DDR interfaces.

    8.13.4.2.4.3 Compatible JEDEC DDR3 Devices

    Best regards,
    Pavel