DM6467 DSP side program not working

Paul Isaac

Other Parts Discussed in Thread: TMS320DM6467

I modified the 'read write ' program for my encoder application(For DM6467 evm). 
But there is a problem in dsp side, that not executing after a particular line of my program.

I gave enough space for code/data in DDR memory.  

This is my memory map configuration,

{
        0,                            /* ENTRY          : Entry number */
        "DSPLINKMEM",                 /* NAME           : Name of the memory region */
        0x8FEF0000,                   /* ADDRPHYS       : Physical address */
        0x8FEF0000,                   /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,                  /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x5000,                       /* SIZE           : Size of the memory region */
        TRUE                          /* SHARED         : Shared access memory? */
    },
    {
        1,                            /* ENTRY          : Entry number */
        "DSPLINKMEM1",                /* NAME           : Name of the memory region */
        0x8FEF5000,                   /* ADDRPHYS       : Physical address */
        0x8FEF5000,                   /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,                  /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0xFB000,                      /* SIZE           : Size of the memory region */
        TRUE                          /* SHARED         : Shared access memory? */
    }, 
    {
        2,                            /* ENTRY          : Entry number */
        "RESETCTRL",                  /* NAME           : Name of the memory region */
        0x8FFF0000,                   /* ADDRPHYS       : Physical address */
        0x8FFF0000,                   /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,                  /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00000080,                   /* SIZE           : Size of the memory region */
        FALSE                         /* SHARED         : Shared access memory? */
    },
    {
        3,                            /* ENTRY          : Entry number */
        "DDR",                        /* NAME           : Name of the memory region */
        0x8FFF0080,                   /* ADDRPHYS       : Physical address */
        0x8FFF0080,                   /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,                  /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x2000000,                    /* SIZE           : Size of the memory region */
        FALSE                         /* SHARED         : Shared access memory? */
    }


Corresponding to this I also modified the .tci file(Increased DDR memory size).


My program using 34KB of shared memory in 'DSPLINKMEM1' memory area.
My dsp executable size is 856KB.


But still my application not working after some lines in dsp side application.   
I don't know whether I have to modify any other configuration files, corresponding to .tci file.


I am compiling the dsp program in linux environment using the make files provided with the examples.


Please help me to solve the problem.
  Thanks in advance.

over 13 years ago

0 Ramsey over 13 years ago

TI__Genius 12025 points

Paul,

Looking at your memory table above, I would summarize you memory map as follows:

8000_0000 - 9FFF_FFFF 2000_0000 ( 512 MB) External Memory
------------------------------------------------------------------------
8FEF_0000 - 8FEF_4FFF       5000 ( 20 KB) DSPLINKMEM
8FEF_5000 - 8FFE_FFFF     F_B000 (1004 KB) DSPLINKMEM1
8FFF_0000 - 8FFF_007F         80 ( 128 B) RESETCTRL
8FFF_0080 - 91FF_0080   200_0000 ( 32 MB) DDR

I don't see anything wrong with this but I do have some comments.

1. Your DDR section rolls over the 256 MB boundary. Does your device have sufficient memory? I think the DM6467 has 512 MB of DDR, but it would be good to confirm this.

2. It looks like you changed the default order of the memory sections. Did you also update the ENTRYID macros as needed? Maybe you could attach your CFG_DM6467GEM_SHMEM.c file to this post.

3. I don't see a memory entry for pool. Are you not using any pools?

4. Have a look at your DSP program's generated map file. You can look at the memory section table to confirm the section placement agrees with the DSPLink's memory map.

5. Maybe the DSP is encountering an exception. Can you attach to the DSP with CCS and inspect the program state? Has the DSP crashed or is it simply spinning in the idle loop waiting for a command from the host?

6. How much memory are you giving to the Linux kernel (i.e. what is the MEM boot arg)?

7. It is not a requirement, but I suggest you align and size the entire DSPLink cumulative memory map on a megabyte boundary (without any holes). This allows more efficient use of the MMU entries. For example, your current memory map size is 33 MB + 128 B and does not start on a megabyte boundary. I might bring it down to the next megabyte boundary and increast the size to 34 MB. Keep in mind that the reset address must stay aligned on a 10-bit boundary. See section 4.4.2.1 of the DM6467 data sheet (TMS320DM6467.pdf).

8FE0_0000 - 91FF_FFFF 220_0000 ( 34 MB) total dsplink memory map

~ Ramsey

0 Paul Isaac over 13 years ago in reply to Ramsey

Intellectual 340 points

Hi Ramsey,

Thanks for your reply.May I address each of your comments.

1. Your DDR section rolls over the 256 MB boundary. Does your device have sufficient memory?

It has got 512MB DDR memory.

2. It looks like you changed the default order of the memory sections. Did you also update the ENTRYID macros as needed?

I didnot change the order , just increased the size of DDR memory.I am attatching the CFG_Davinci_DM6467.c and dsplink-dm6467-base.tci

files along with this.Please look through it .

Fullscreen 2620.CFG_Davinci_DM6467.c.txt Download

/** ============================================================================
 *  @file   CFG_Davinci_DM6467.c
 *
 *  @path   $(DSPLINK)/config/all/
 *
 *  @desc   Defines the configuration information for DSP/BIOS LINK for the
 *          DM6467 platform.
 *
 *  @ver    1.50
 *  ============================================================================
 *  Copyright (c) Texas Instruments Incorporated 2002-2007
 *
 *  Use of this software is controlled by the terms and conditions found in the
 *  license agreement under which this software has been supplied or provided.
 *  ============================================================================
 */


/*  ----------------------------------- DSP/BIOS LINK Headers       */
#include <dsplink.h>
#include <procdefs.h>


#if defined (__cplusplus)
EXTERN "C" {
#endif /* defined (__cplusplus) */


/** ============================================================================
 *  @name   LINKCFG_gppOsObject
 *
 *  @desc   Extern declaration for the OS-specific configuration object.
 *          NOTE: This object is defined in the GPP OS-specific configuration
 *          file CFG_<GPPOS>.c.
 *          The type of this object is also OS-specific and is defined in
 *          linkcfgdefs_os.h for each GPP OS.
 *  ============================================================================
 */
extern LINKCFG_GppOs LINKCFG_gppOsObject ;

/** ============================================================================
 *  @name   LINKCFG_gppObject
 *
 *  @desc   Configuration object for the GPP.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Gpp  LINKCFG_gppObject = {
    "ARM9",                         /* NAME           : Name of the GPP */
    16,                             /* MAXMSGQS       : Maximum MSGQs that can be opened */
    16,                             /* MAXCHNLQUEUE   : Maximum Queue Length for all channels */
    (Uint32) -1,                    /* POOLTABLEID    : ID of the POOL table (-1 if not needed) */
    0,                              /* NUMPOOLS       : Number of POOLs supported */
    (Uint32) -1,                    /* PROBERTCID     : Real Time Clock ID for PROBE */
    (Uint32) -1                     /* PROBEINTID     : Interrupt ID for PROBE */
} ;

/** ============================================================================
 *  @name   LINKCFG_dspObjects
 *
 *  @desc   Array of configuration objects for the DSPs in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Dsp  LINKCFG_dspObjects [] =
{
    {
        "Gem",                 /* NAME           : Name of the DSP */
        DspArch_C64x,          /* ARCHITECTURE   : DSP architecture */
        "COFF",                /* LOADERNAME     : Name of the DSP executable loader */
        FALSE,                 /* AUTOSTART      : Autostart the DSP (Not supported) */
        "DEFAULT.OUT",         /* EXECUTABLE     : Executable for autostart */
        TRUE,                  /* DOPOWERCTRL    : Link does the Power Ctrl of DSP. */
        0x8FF00020,            /* RESUMEADDR     : Resume address */
        0x8FF00000,            /* RESETVECTOR    : Reset Vector for the DSP */
        0x80,                  /* RESETCODESIZE  : Size of code at DSP Reset Vector */
        1,                     /* MADUSIZE       : DSP Minimum Addressable Data Unit */
        (Uint32) -1,           /* CPUFREQ        : DSP Frequency (in KHz), -1 if default setting is to be used */
        Endianism_Little,      /* ENDIAN         : DSP Endianism */
        FALSE,                 /* WORDSWAP       : Words must be swapped when writing to memory */
        0,                     /* MEMTABLEID     : ID of the memory table used */
        6,                     /* MEMENTRIES     : Number of entries in memory table */
        0                      /* LINKDRVID      : ID of the link driver used */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_memTable_00
 *
 *  @desc   Memory table ID 0.
 *  ============================================================================
 */
STATIC CONST LINKCFG_MemEntry  LINKCFG_memTable_00 [] =
{
    {
        0,                     /* ENTRY          : Entry number */
        "DSPLINKMEM",          /* NAME           : Name of the memory region */
        0x8FE00000,            /* ADDRPHYS       : Physical address */
        0x8FE00000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x5000,                /* SIZE           : Size of the memory region */
        TRUE                   /* SHARED         : Shared access memory? */
    },
    {
        1,                     /* ENTRY          : Entry number */
        "DSPLINKMEM1",         /* NAME           : Name of the memory region */
        0x8FE05000,            /* ADDRPHYS       : Physical address */
        0x8FE05000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0xFB000,               /* SIZE           : Size of the memory region */
        TRUE                   /* SHARED         : Shared access memory? */
    },
    {
        2,                     /* ENTRY          : Entry number */
        "RESETCTRL",           /* NAME           : Name of the memory region */
        0x8FF00000,            /* ADDRPHYS       : Physical address */
        0x8FF00000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00000080,            /* SIZE           : Size of the memory region */
        FALSE                  /* SHARED         : Shared access memory? */
    },
    {
        3,                     /* ENTRY          : Entry number */
        "DDR",                 /* NAME           : Name of the memory region */
        0x8FF00080,            /* ADDRPHYS       : Physical address */
        0x8FF00080,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x10000000,               /* SIZE           : Size of the memory region */
        FALSE                  /* SHARED         : Shared access memory? */
    },
    {
        4,                     /* ENTRY          : Entry number */
        "DSPIRAM",             /* NAME           : Name of the memory region */
        0x11818000,            /* ADDRPHYS       : Physical address */
        0x11818000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x20000,                /* SIZE           : Size of the memory region */
        FALSE                  /* SHARED         : Shared access memory? */
    },
    {
        5,                     /* ENTRY          : Entry number */
        "DSPL1DRAM",           /* NAME           : Name of the memory region */
        0x11F00000,            /* ADDRPHYS       : Physical address */
        0x11F00000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x8000,                /* SIZE           : Size of the memory region */
        FALSE                  /* SHARED         : Shared access memory? */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_memTables
 *
 *  @desc   Array of memory tables in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_MemEntry * LINKCFG_memTables [] =
{
    LINKCFG_memTable_00        /* Memory Table 0 */
} ;

/** ============================================================================
 *  @name   LINKCFG_linkDrvObjects
 *
 *  @desc   Array of Link driver objects in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_LinkDrv  LINKCFG_linkDrvObjects [] =
{
    {
        "SHMDRV",              /* NAME           : Name of the link driver */
        (Uint32) 100000000,    /* HSHKPOLLCOUNT  : Poll value for which handshake waits (-1 if infinite) */
        (Uint32) 1,            /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        0,                     /* IPSTABLEID     : ID of the IPS table used */
        1,                     /* IPSENTRIES     : Number of IPS supported */
        0,                     /* POOLTABLEID    : ID of the POOL table */
        1,                     /* NUMPOOLS       : Number of POOLs supported */
        0,                     /* DATATABLEID    : ID of the data driver table */
        1,                     /* NUMDATADRV     : Number of data drivers supported */
        0,                     /* MQTID          : ID of the MQT */
        0,                     /* RINGIOTABLEID  : RingIO Table Id used for this DSP */
        0,                     /* MPLISTTABLEID  : MpList Table Id used for this DSP */
        0                      /* MPCSTABLEID    : MPCS Table ID used for this DSP */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_ipsTable_00
 *
 *  @desc   IPS table ID 0.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Ips  LINKCFG_ipsTable_00 [] =
{
    {
        "IPS",                 /* NAME           : Name of the Inter-Processor-Signaling component */
        (Uint32) 32,           /* NUMIPSEVENTS   : Number of IPS events to be supported */
        (Uint32) 0,            /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        (Uint32) 45,           /* GPPINTID       : Interrupt no. to used by the IPS on GPP-side. (-1 if uni-directional to DSP) */
        (Uint32) 16,           /* DSPINTID       : Interrupt no. to used by the IPS on DSP-side. (-1 if uni-directional to GPP) */
        (Uint32) 4,            /* DSPINTVECTORID : Interrupt vector no. to used by the IPS on DSP-side. (-1 if uni-directional to GPP) */
        (Uint32) 50000000,     /* ARGUMENT1      : Poll value for which IPS waits while sending event (-1 if infinite) */
        0                      /* ARGUMENT2      : Second IPS-specific argument */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_ipsTables
 *
 *  @desc   Array of IPS tables in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Ips * LINKCFG_ipsTables [] =
{
    LINKCFG_ipsTable_00        /* IPS Table 0 */
} ;

/** ============================================================================
 *  @name   LINKCFG_poolTable_00
 *
 *  @desc   Pool table ID 0.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Pool  LINKCFG_poolTable_00 [] =
{
    {
        "SMAPOOL",             /* NAME           : Name of the pool */
        (Uint32) 1,            /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        (Uint32) 0x70000,      /* POOLSIZE       : Size of the pool (-1 if not needed) */
        (Uint32) -1,           /* IPSID          : ID of the IPS used */
        (Uint32) -1,           /* IPSEVENTNO     : IPS Event number associated with POOL */
        0x0,                   /* ARGUMENT1      : First Pool-specific argument */
        0x0                    /* ARGUMENT2      : Second Pool-specific argument */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_poolTables
 *
 *  @desc   Array of Pool tables in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Pool * LINKCFG_poolTables [] =
{
    LINKCFG_poolTable_00       /* Pool Table 0 */
} ;

/** ============================================================================
 *  @name   LINKCFG_dataTable_00
 *
 *  @desc   Data driver table ID 0.
 *  ============================================================================
 */
STATIC CONST LINKCFG_DataDrv  LINKCFG_dataTable_00 [] =
{
    {
        "ZCPYDATA",            /* NAME           : Name of the data driver */
        0,                     /* BASECHANNELID  : Base channel ID for the driver */
        16,                    /* NUMCHANNELS    : Number of channels supported */
        16384,                 /* MAXBUFSIZE     : Maximum size of buffer supported (-1 if no limit) */
        (Uint32) 1,            /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        0,                     /* POOLID         : Pool id for allocating buffers */
        1,                     /* QUEUELENGTH    : Queue length for the data driver */
        0,                     /* IPSID          : ID of the IPS used */
        2,                     /* IPSEVENTNO     : IPS Event number associated with data Driver */
        0x0,                   /* ARGUMENT1      : First data driver specific argument */
        0x0                    /* ARGUMENT2      : Second data driver specific argument */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_dataTables
 *
 *  @desc   Array of Data driver tables in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_DataDrv * LINKCFG_dataTables [] =
{
    LINKCFG_dataTable_00       /* Data Table 0 */
} ;

/** ============================================================================
 *  @name   LINKCFG_mqtObjects
 *
 *  @desc   Array of Message Queue Transport objects in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Mqt  LINKCFG_mqtObjects [] =
{
    {
        "ZCPYMQT",             /* NAME           : Name of the Message Queue Transport */
        (Uint32) 1,            /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        (Uint32) -1,           /* MAXMSGSIZE     : Maximum message size supported (-1 if no limit) */
        0,                     /* IPSID          : ID of the IPS used */
        1,                     /* IPSEVENTNO     : IPS Event number associated with MQT */
        0x0,                   /* ARGUMENT1      : First MQT-specific argument */
        0x0                    /* ARGUMENT2      : Second MQT-specific argument */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_ringIoObjects
 *
 *  @desc   Array of RINGIO objects in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_RingIo  LINKCFG_ringIoObjects [] =
{
    {
        "RINGIOTABLE",         /* NAME           : Name of the RingIO Table */
        0,                     /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        64,                    /* NUMENTRIES     : Number of RingIO entries supported */
        0,                     /* IPSID          : ID of the IPS used */
        0                      /* IPSEVENTNO     : IPS Event number associated with RingIO */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_mplistObjects
 *
 *  @desc   Array of MPLIST objects in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_MpList  LINKCFG_mplistObjects [] =
{
    {
        "MPLISTTABLE",         /* NAME           : Name of the MpList Table */
        1,                     /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        64,                    /* NUMENTRIES     : Number of MpList entries supported */
        (Uint32) -1,           /* IPSID          : ID of the IPS used */
        (Uint32) -1            /* IPSEVENTNO     : IPS Event number associated with MpList */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_mpcsObjects
 *
 *  @desc   Array of MPCS objects in the system.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Mpcs  LINKCFG_mpcsObjects [] =
{
    {
        "MPCS",                /* NAME           : Name of the MPCS Table */
        1,                     /* MEMENTRY       : Memory entry ID (-1 if not needed) */
        256,                   /* NUMENTRIES     : Number of MPCS entries supported */
        (Uint32) -1,           /* IPSID          : ID of the IPS used */
        (Uint32) -1            /* IPSEVENTNO     : IPS Event number associated with MPCS */
    }
} ;

/** ============================================================================
 *  @name   LINKCFG_gppObject
 *
 *  @desc   Configuration object for the GPP.
 *  ============================================================================
 */
STATIC CONST LINKCFG_Log  LINKCFG_logObject = {
    FALSE,             /* GDMSGQPUT         : GPP->DSP MSG Transfer  - MSGQ_put call */
    FALSE,             /* GDMSGQSENDINT     : GPP->DSP MSG Transfer  - GPP sends interrupt */
    FALSE,             /* GDMSGQISR         : GPP->DSP MSG Transfer  - DSP receives interrupt */
    FALSE,             /* GDMSGQQUE         : GPP->DSP MSG Transfer  - Message queued at DSP */
    FALSE,             /* DGMSGQPUT         : DSP->GPP MSG Transfer  - MSGQ_put call */
    FALSE,             /* DGMSGQSENDINT     : DSP->GPP MSG Transfer  - DSP sends interrupt */
    FALSE,             /* DGMSGQISR         : DSP->GPP MSG Transfer  - GPP receives interrupt */
    FALSE,             /* DGMSGQQUE         : DSP->GPP MSG Transfer  - Message queued at GPP */
    FALSE,             /* GDCHNLISSUESTART  : GPP->DSP CHNL Transfer - Entering inside ISSUE call */
    FALSE,             /* GDCHNLISSUEQUE    : GPP->DSP CHNL Transfer - ISSUE: Buffer is queued in internal structure on GPP */
    FALSE,             /* GDCHNLISSUECOMPL  : GPP->DSP CHNL Transfer - ISSUE call completed */
    FALSE,             /* GDCHNLXFERSTART   : GPP->DSP CHNL Transfer - Initiating a buffer transfer by GPP */
    FALSE,             /* GDCHNLXFERPROCESS : GPP->DSP CHNL Transfer - Actual transfer of buffer is going to take place */
    FALSE,             /* GDCHNLXFERCOMPL   : GPP->DSP CHNL Transfer - Buffer transfer is complete */
    FALSE,             /* GDCHNLRECLSTART   : GPP->DSP CHNL Transfer - Entering RECLAIM call */
    FALSE,             /* GDCHNLRECLPEND    : GPP->DSP CHNL Transfer - RECLAIM: Wait on a semaphore */
    FALSE,             /* GDCHNLRECLPOST    : GPP->DSP CHNL Transfer - RECLAIM: Posting the Semaphore */
    FALSE,             /* GDCHNLRECLCOMPL   : GPP->DSP CHNL Transfer - RECLAIM call completed */
    FALSE,             /* DGCHNLISSUEQUE    : DSP->GPP CHNL Transfer - ISSUE: Buffer is queued in internal structure on DSP */
    FALSE,             /* DGCHNLXFERSTART   : DSP->GPP CHNL Transfer - Initiating a buffer transfer by DSP */
    FALSE,             /* DGCHNLXFERPROCESS : DSP->GPP CHNL Transfer - Actual transfer of buffer is going to take place */
    FALSE,             /* DGCHNLXFERCOMPL   : DSP->GPP CHNL Transfer - Buffer transfer is complete */
    FALSE,             /* DGCHNLRECLPEND    : DSP->GPP CHNL Transfer - RECLAIM: Wait on a semaphore */
    FALSE,             /* DGCHNLRECLPOST    : DSP->GPP CHNL Transfer - RECLAIM: Posting the Semaphore */
    10,                /* MSGIDRANGESTART   : MSG ID range: lower limit */
    20                 /* MSGIDRANGEEND     : MSG ID range: upper limit */
} ;

/** ============================================================================
 *  @name   LINKCFG_config
 *
 *  @desc   DSP/BIOS LINK configuration structure.
 *  ============================================================================
 */
CONST LINKCFG_Object  LINKCFG_config = {
    (LINKCFG_Gpp *)       &LINKCFG_gppObject,     /* GPPOBJECT      : GPP object */
    1,                                            /* NUMDSPS        : Number of DSPs in the system */
    (LINKCFG_Dsp *)       LINKCFG_dspObjects,     /* DSPOBJECTS     : Array of DSP objects */
    (LINKCFG_LinkDrv *)   LINKCFG_linkDrvObjects, /* LINKDRVOBJECTS : Array of Link Driver objects */
    1,                                            /* NUMMEMTABLES   : Number of memory tables */
    (LINKCFG_MemEntry **) LINKCFG_memTables,      /* MEMTABLES      : Array of Memory tables */
    1,                                            /* NUMIPSTABLES   : Number of IPS tables */
    (LINKCFG_Ips **)      LINKCFG_ipsTables,      /* IPSTABLES      : Array of IPS tables */
    1,                                            /* NUMPOOLTABLES  : Number of POOL tables */
    (LINKCFG_Pool **)     LINKCFG_poolTables,     /* POOLTABLES     : Array of Pool tables */
    1,                                            /* NUMDATATABLES  : Number of data tables */
    (LINKCFG_DataDrv **)  LINKCFG_dataTables,     /* DATATABLES     : Array of data tables */
    1,                                            /* NUMMQTS        : Number of MQTs */
    (LINKCFG_Mqt *)       LINKCFG_mqtObjects,     /* MQTOBJECTS     : Array of MQT objects */
    1,                                            /* NUMRINGIOTABLES: Number of RINGIO tables */
    (LINKCFG_RingIo *)    LINKCFG_ringIoObjects,  /* RINGIOOBJECTS  : Array of RINGIO objects */
    1,                                            /* NUMMPLISTTABLES: Number of MPLIST tables */
    (LINKCFG_MpList *)    LINKCFG_mplistObjects,  /* MPLISTOBJECTS  : Array of MPLIST objects */
    1,                                            /* NUMMPCSTABLES  : Number of MPCS tables */
    (LINKCFG_Mpcs *)      LINKCFG_mpcsObjects,    /* MPCSOBJECTS    : Array of MPCS objects */
    (LINKCFG_Log *)       &LINKCFG_logObject,     /* LOGOBJECT      : Pointer to LOG object */
    (LINKCFG_GppOs *)     &LINKCFG_gppOsObject    /* GPPOSOBJECT    : Pointer to GPP OS object */
} ;


#if defined (__cplusplus)
}
#endif /* defined (__cplusplus) */

Fullscreen 2526.dsplink-dm6467-base.tci.txt Download

/** ============================================================================
 *  @file   dsplink-dm6467-base.tci
 *
 *  @path   $(DSPLINK)/dsp/inc/DspBios/Davinci/DM6467/
 *
 *  @desc   This file defines base configuration for DSP/BIOS LINK.
 *
 *  @ver    1.50
 *  ============================================================================
 *  Copyright (c) Texas Instruments Incorporated 2002-2007
 *
 *  Use of this software is controlled by the terms and conditions found in the
 *  license agreement under which this software has been supplied or provided.
 *  ============================================================================
 */


/*  ============================================================================
 *  Load assert support
 *  ============================================================================
 */
utils.importFile("assert.tci");


params = {
    clockRate: 594,
    catalogName: "ti.catalog.c6000",
    deviceName: "DM6467",
};

/*  ============================================================================
 *  Load base TCI file.
 *  ============================================================================
 */
utils.loadPlatform("ti.platforms.generic", params);

/*  ============================================================================
 *  Enable common BIOS features used by all examples
 *  ============================================================================
 */
bios.disableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.disableRtdx(prog);
bios.enableTskManager(prog);

/*  ============================================================================
 *  GBL
 *  ============================================================================
 */
prog.module("GBL").ENABLEALLTRC    = false ;
prog.module("GBL").PROCID          = 0 ;

prog.module("GBL").C64PLUSCONFIGURE   = true ;
prog.module("GBL").C64PLUSL1DCFG      = "32k" ;
prog.module("GBL").C64PLUSMAR128to159 = 0x00008000 ;

/*  ============================================================================
 *  MEM
 *  ============================================================================
 */
prog.module("MEM").STACKSIZE = 0x8000 ;

/*  ============================================================================
 *  MEM : DSPLINKMEM
 *  ============================================================================
 */
var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM");
DSPLINKMEM.base             = 0x8FE00000;
DSPLINKMEM.len              = 0x100000;
DSPLINKMEM.createHeap       = false;
DSPLINKMEM.comment          = "DSPLINKMEM";

/*  ============================================================================
 *  MEM : RESET_VECTOR
 *  ============================================================================
 */
var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");
RESET_VECTOR.base        = 0x8FF00000;
RESET_VECTOR.len         = 0x00000080;
RESET_VECTOR.space       = "code/data";
RESET_VECTOR.createHeap  = false;
RESET_VECTOR.comment     = "RESET_VECTOR";

/*  ============================================================================
 *  MEM : DDR
 *  ============================================================================
 */
var DDR = prog.module("MEM").create("DDR");
DDR.base             = 0x8FF00080;
DDR.len              = 0x10000000;
DDR.space            = "code/data";
DDR.createHeap       = true;
DDR.heapSize         = 0x80000;
DDR.comment          = "DDR";

/*  ============================================================================
 *  Workaround for SDSCM00018346 - Timer frequency on DM6467 should be set
 *  to ARM CPU/2
 *  ============================================================================
 */
prog.module("CLK").SPECIFYRATE = true;
prog.module("CLK").INPUTCLK = 148.5;

3. I don't see a memory entry for pool. Are you not using any pools?

I am not using any memory pools but PROC and MSGQ.

4.You can look at the memory section table to confirm the section placement agrees with the DSPLink's memory map.

I checked it and got confirmed.

5.Has the DSP crashed or is it simply spinning in the idle loop waiting for a command from the host?

When I try to put return statement before the codec lines causing problem,its working.Initially I thought the problem might be in shortage of code space.

But even when I increased the DDR length where the code space is been allocated,problem is still there.For the control structures and the input/output buffers

I am using 'DSPLINKMEM1'(34KB).Please verify the attached files for any memory conflicts.

6. How much memory are you giving to the Linux kernel (i.e. what is the MEM boot arg)?

120MB memory space is given.

Expecting your reply .Thanks in advance.

0 Ramsey over 13 years ago in reply to Paul Isaac

TI__Genius 12025 points

Paul,

I studied your configuration files and did not find anything wrong. However, the memory map does not match up with your original post, but maybe that was an early test. At any rate, I have only some suggestions.

1. On the dsp side, the cache-ability of external memory is determined by the mar bits. Each mar bit controls the cache-ability of a 16 MB block of memory. In the original configuration, only one bit is set. Since you increased the DDR memory by 256 MB, you would need to set the corresponding bits. This would only effect the performance of your program since the code assumes the memory is cached. If you want to make your DDR cacheable, set the mar bits as follows in your dsplink-dm6467-base.tci file.

prog.module("GBL").C64PLUSMAR128to159 = 0xFFFF8000 ;

2. What dsp address are you using? This address must be visible to both the dsp and the host. The original examples uses 0x8FEF0000 which is near the end of DSPLINKMEM1. Notice that in the CFG_Davinci_DM6467.c file this memory section has the shared property set to true. But the DDR memory section has this set to false. This means that you cannot use any address from the DDR memory section. You would not want to set the shared property to true for the DDR memory section because this would cause the Linux kernel to map the full 256 MB into the kernel virtual address space. This would most likely fail due to lack of virtual memory.

3. In order to gain more insight into the failure, I suggest to post on the Embedded Software > BIOS forum for help on how to turn on BIOS tracing to see how far your program gets before crashing.

~ Ramsey

0 Paul Isaac over 13 years ago in reply to Ramsey

Intellectual 340 points

Hi Ramsey,

Thank you for your reply.

I was able to run the code.For that I had to put a delay in my dsp side program. I am attaching a simplified flow diagram of my application.

After the MSGQ_put() which follows the Encode_frame() call, I put a delay .Then the program runs smoothly.But the actual code cannot afford such a delay . Can you figure out the problem causing this.

0 Ramsey over 13 years ago in reply to Paul Isaac

TI__Genius 12025 points

Paul,

My only thought is that the message queue interrupt from ARM to DSP is not working. Without the delay on the DSP side, I'm guessing that the task calls MSGQ_get before the next message arrives. This would cause the task to suspend and the idle task starts running (assuming there are no other tasks ready on the DSP). When the host calls MSGQ_put, it would raise the ARM to DSP interrupt which is supposed to wake up the suspended task which had called MSGQ_get. Maybe this is not working. Would you check the DSP's IFR register to see if there is a pending interrupt which was not taken?

When you add the delay, maybe this gives the ARM sufficient time to send the message so when the DSP finally calls MSGQ_get there is already a message in the queue. In this case, the task would not suspend, and the call would return with the message.

One easy way to test this is to call MSGQ_get with a timeout of zero. This will cause MSGQ_get to never block (it is polling), it will return immediately with or without a message. Do this in a loop until MSGQ_get returns with DSP_SOK. If this fixes the problem, then there must be something wrong with the interrupt configuration.

~ Ramsey

0 Paul Isaac over 13 years ago in reply to Ramsey

Intellectual 340 points

Hi Ramsey,

Thanks for your reply.As you have suggested the problem is in MSGQ_get(). So I tried it with in a 'do while' loop and with a time out of zero.

Is there any issue in using this idea?? since your last statement confuses me.

"If this fixes the problem, then there must be something wrong with the interrupt configuration".

Is there anyway to put a timeout for the MSGQ_get rather than using the 'do while' loop??

Mentioned below are attributes I have given for the MSGQ.

        SEM_new (&(info->notifyDspSemObj), 0) ;

        msgqAttrs.notifyHandle = &(info->notifyDspSemObj) ;
        msgqAttrs.pend         = (MSGQ_Pend) SEM_pendBinary ;
        msgqAttrs.post         = (MSGQ_Post) SEM_postBinary ;

 Expecting your reply.

Thanks

0 Ramsey over 13 years ago in reply to Paul Isaac

TI__Genius 12025 points

Paul,

You can pass a timeout value to MSGQ_get() as the second argument; the timeout value is in milliseconds.

My comment suggests that your original use of MSGQ_get should also be working. If the DSP calls MSGQ_get before the message arrives, the task should block. When the message is delivered by the transport, it should signal the block task which would then resume execution. It seems that this is not working for you. This points to a problem with either the transport configuration or the interrupt configuration.

It is more efficient to use the blocking call to MSGQ_get instead of using a timeout. However, as long as you try again when there is no message, it should be functionally equivalent.

What version of DSPLink are you using?

Please check your transport configuration. You are probably using ZCPYMQT in your CFG_Davinci_DM6467.c file. On the DSP side, you need to configure a transport object for the DSP entry in the transports array. Please check your readwrite_config.c file.

~ Ramsey

0 Paul Isaac over 13 years ago in reply to Ramsey

Intellectual 340 points

Hi Ramsey,

Thank you for your reply,

As you said the problem was with the MSGQ_get() function in the dsp side. Since the MSGQ_get() functios fails , dsp side remains in the idle state. Initially I didn't put any code for handling such a condition. Any way using timeout in the MSGQ_get() function works fine for me .

I am using DSPLink 1.5. Is there any issue with this ?.

Since my application is running fine, with timeout in MSGQ_get(), whether it needed to change the transport configuration ?

Thanks

0 Ramsey over 13 years ago in reply to Paul Isaac

TI__Genius 12025 points

Paul,

Your version of DSPLink sounds fine.

If your application is running adequately, then you don't need to modify the transport. However, for complete correctness, you would want to find out why MSGQ_get() does not behave correctly with timeout = 0. It might be the transport configuration or the interrupt configuration. It's up to you how far you want to dig in.

~ Ramsey

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DM6467 DSP side program not working