OMAP-L138 SATA Interface Clock Source - LVPECL instead of LVDS

fdm

Hi all,

The OMAP-L138 DS states that "the SATA interface requires a LVDS differential clock source to be provided at signals SATA_REFCLKP and SATA_REFCLKN".

The last DS revision (sprs586b) specifies only the minimum value (250 mV) of the Differential Clock Input voltage.

What is the maximum allowable value?

And can the LVPECL clock source be used taking into account the capacitive coupling recommended for that clock input?

over 14 years ago

0 Clay Turner over 14 years ago

TI__Expert 3540 points

The peak-to-peak differential voltage input on the clock pins 250 mV to 2V peak-to-peak. LVPECL has a Vol of 1.6V and Voh of 2.4V, which is a total differential voltage of 0.8V pk-to-pk so that should be fine when ac-coupled.

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OMAP-L138 SATA Interface Clock Source - LVPECL instead of LVDS