GPMC can write but cannot read

I am using the gpmc to read/write fpga. And the fpga connect the cs to GPMC_CSN1. With the following configuration, when i write the fpga, the cs and we have the signal. But when i read the fpga, the cs and oe have no signal. so i checked the configuration , but cannot find what the problem is. Can anybody help me? My configuration is as following: int GPMCFPGAMInit(void) { int retval=1; U32 conf; U32 baseAddr; U32 cs; volatile U32 timeOut; cs = 1; conf = SOC_GPMC_0_REGS; timeOut =0xFFF; baseAddr = GPMC_CHIP_SELECT_1; /* GPMC Module configuration */ GPMCModuleSoftReset(baseAddr); while((GPMCModuleResetStatusGet(baseAddr) != 1) && (timeOut != 0)) { timeOut--; } if(timeOut == 0) { return 0; } GPMCIdleModeSelect(baseAddr, GPMC_IDLEMODE_NOIDLE); /* Disable all interrupts */ GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT); GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT); GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT); GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT); /* Timeout control disable */ GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE); /* Set the wait pin polarity */ GPMCWaitPinSelect(baseAddr, cs, GPMC_WAIT_PIN0); GPMCWaitPinPolaritySelect(baseAddr, GPMC_WAIT_PIN0, GPMC_WAIT_PIN_POLARITY_LOW); GPMCWriteProtectPinLevelCtrl(baseAddr, GPMC_WP_PIN_LEVEL_HIGH); GPMCLimitedAddrDevSupportConfig(baseAddr, GPMC_LIMITEDADDRESS_SUPPORT_ENABLE); GPMCCSConfig(baseAddr, cs, GPMC_CS_DISABLE); GPMCTimeParaGranularitySelect(baseAddr, cs, GPMC_TIMEPARAGRANULARITY_X2); GPMCDevTypeSelect(baseAddr, cs, GPMC_DEVICETYPE_NORLIKE); GPMCDevSizeSelect(baseAddr, cs, GPMC_DEVICESIZE_16BITS); GPMCAddrDataMuxProtocolSelect(baseAddr, cs, GPMC_MUXADDDATA_NOMUX); GPMCWriteTypeSelect(baseAddr, cs, GPMC_WRITETYPE_ASYNC); GPMCReadTypeSelect(baseAddr, cs, GPMC_READTYPE_ASYNC); GPMCAccessTypeSelect(baseAddr, cs, GPMC_MODE_WRITE, GPMC_ACCESSTYPE_SINGLE); GPMCAccessTypeSelect(baseAddr, cs, GPMC_MODE_READ, GPMC_ACCESSTYPE_SINGLE); GPMCBaseAddrSet(baseAddr, cs, 0x10000000 >> 24); GPMCMaskAddrSet(baseAddr, cs, GPMC_CS_SIZE_128MB); conf = GPMC_CS_TIMING_CONFIG(NAND_CSWROFFTIME, NAND_CSRDOFFTIME, 0, NAND_CSONTIME); GPMCCSTimingConfig(baseAddr, cs, conf); conf = GPMC_ADV_TIMING_CONFIG(NAND_ADVAADMUXWROFFTIME, NAND_ADVAADMUXRDOFFTIME, NAND_ADVWROFFTIME, NAND_ADVRDOFFTIME, 0, NAND_ADVAADMUXONTIME, NAND_ADVONTIME); GPMCADVTimingConfig(baseAddr, cs, conf); conf = GPMC_WE_OE_TIMING_CONFIG(NAND_WEOFFTIME, 0, NAND_WEONTIME, NAND_OEAADMUXOFFTIME, NAND_OEOFFTIME, 0, NAND_OEAADMUXONTIME, NAND_OEONTIME); GPMCWEAndOETimingConfig(baseAddr, cs, conf); conf = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG( NAND_RDCYCLETIME, NAND_WRCYCLETIME, NAND_RDACCESSTIME, NAND_PAGEBURSTACCESSTIME); GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, cs, conf); conf = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG( NAND_CYCLE2CYCLEDELAY, NAND_CYCLE2CYCLESAMECSEN, NAND_CYCLE2CYCLEDIFFCSEN, NAND_BUSTURNAROUND); GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, cs, conf); GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, cs, NAND_WRACCESSTIME, NAND_WRDATAONADMUXBUS); GPMCCSConfig(baseAddr, cs, GPMC_CS_ENABLE); return (retval); } static void MMUConfigAndEnable(void) { /* ** Define DDR memory region of AM335x. DDR can be configured as Normal ** memory with R/W access in user/privileged modes. The cache attributes ** specified here are, ** Inner - Write through, No Write Allocate ** Outer - Write Back, Write Allocate */ REGION regionDdr = { MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW, (unsigned int*)pageTable }; /* ** Define internal SRAM region of AM335x. Same Attributes of DDR region given. */ REGION regionSram = { MMU_PGTYPE_SECTION, START_ADDR_SRAM, NUM_SECTIONS_SRAM, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW, (unsigned int*)pageTable }; /* ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given. */ REGION regionOcmc = { MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW, (unsigned int*)pageTable }; /* ** Define Device Memory Region. The region between OCMC and DDR is ** configured as device memory, with R/W access in user/privileged modes. ** Also, the region is marked 'Execute Never'. */ REGION regionDev = { MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV, MMU_MEMTYPE_DEVICE_SHAREABLE, MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER, (unsigned int*)pageTable }; #if 1 /* ** Define NAND Region. The region is ** configured as device memory, with R/W access in user/privileged modes. ** Also, the region is marked 'Execute Never'. */ REGION regionNand = { MMU_PGTYPE_SECTION, START_ADDR_NAND, NUM_SECTIONS_NAND, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WT_NOWA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER, (unsigned int*)pageTable }; #endif #if 1 /* ** Define FPGA(GPMC) Region. The region is ** configured as device memory, with R/W access in user/privileged modes. ** Also, the region is marked 'Execute Never'. */ REGION regionFPGA = { MMU_PGTYPE_SECTION, 0x10000000, 128, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WT_NOWA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER, (unsigned int*)pageTable }; #endif /* Initialize the page table and MMU */ MMUInit((unsigned int*)pageTable); /* Map the defined regions */ MMUMemRegionMap(&regionDdr); MMUMemRegionMap(&regionSram); MMUMemRegionMap(&regionOcmc); MMUMemRegionMap(&regionDev); #if 1 MMUMemRegionMap(&regionNand); MMUMemRegionMap(&regionFPGA); #endif /* Now Safe to enable MMU */ MMUEnable((unsigned int*)pageTable); }