Hi,
Thank you for your time.
I have added utils, drive, platform and systems
I cannot get the interrupts going for Timer (or uart).
On further investigation i found that the timer module is working just fine and is giving a overflow status.
The issue is with CPSR resistor in the core.
I am unable to enable interrupts by resetting the IRQ bit in the CPSR resistor.
Where R0 = 0x40000110
CPSR = 0x40000190
When i do a msr CPSR, r0
I still get CPSR = 0x40000190
IRQ is disabled...
I am sure that I am missing something here,.. can anyone please help
Code below for reference -
#include "dmtimer.h"
#include "interrupt.h"
#include "gpio_v2.h"
#include "soc_AM335x.h"
#include "beaglebone.h"
static void hardware_init();
static void timer_init();
static void timer_config(unsigned long, unsigned long);
static void isr_timer2();
int main(void) {
// Set up hardware and peripherals.
hardware_init();
// Configure timer settings
timer_config(0xF0000000u, 0xF0000000u);
timer_init();
// XXX: Turn on LED
GPIOPinWrite(SOC_GPIO_1_REGS, (23), GPIO_PIN_HIGH);
// Enable timer interrupt
DMTimerIntEnable(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_EN_FLAG);
// Turn on actual timer
DMTimerEnable(SOC_DMTIMER_2_REGS);
asm(" mrs r0, CPSR");
asm(" bic r0, r0, #0x80");
asm(" msr CPSR, r0");
// Loop forever- all work takes place in ISRs.
while(1);
}
static void hardware_init() {
// Configure GPIO/LED
GPIO1ModuleClkConfig();
GPIO1Pin23PinMuxSetup();
GPIOModuleEnable(SOC_GPIO_1_REGS);
GPIOModuleReset(SOC_GPIO_1_REGS);
/* Set GPIO 1.23 as output */
GPIODirModeSet(SOC_GPIO_1_REGS, (23), GPIO_DIR_OUTPUT);
}
static void timer_init() {
// Set up the configuration for the hardware timer.
/* Enable clocks for DMTimer2 */
DMTimer2ModuleClkConfig();
/* Initialize ARM interrupt controller (AINTC) */
IntAINTCInit();
/* Register our ISR to DMTimer2's interrupt. */
IntRegister(SYS_INT_TINT2, isr_timer2);
/* Set the DMTimer2's interrupt priority to 0. */
IntPrioritySet(SYS_INT_TINT2, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the DMTimer2 interrupt. */
IntSystemEnable(SYS_INT_TINT2);
/* Enable IRQ in CPSR (ARM program status register) */
// IntMasterIRQEnable();
}
static void timer_config(unsigned long initial, unsigned long reload) {
// Configure timer
// Note that instead of doing a count from 0 to some compare value, we are
// preloading the timer with a given value and watching for it to overflow,
// which is functionally identical.
/* Configure the timer mode. */
// Modes: autoreload (selected) versus one-shot mode. Does the timer automatically reset itself?
// compare versus overflow (selected) mode. Does the timer ISR trip on equality to a value, or on overflow?
DMTimerModeConfigure(SOC_DMTIMER_2_REGS, DMTIMER_AUTORLD_NOCMP_ENABLE);
/* Load initial counter value into timer. */
DMTimerCounterSet(SOC_DMTIMER_2_REGS, initial);
/* Load reload counter value into timer, the value the timer gets every time it is reset. */
DMTimerReloadSet(SOC_DMTIMER_2_REGS, reload);
}
// Interrupt vector for BeagleBone timer
static void isr_timer2() {
static short int mode = 0;
/* Disable the DMTimer interrupt */
DMTimerIntDisable(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_EN_FLAG);
/* Clear the interrupt flags (IF) status */
DMTimerIntStatusClear(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_IT_FLAG);
/* *********** ISR TASKS BEGIN *********** */
if (mode == 0) {
// Turn on LED
GPIOPinWrite(SOC_GPIO_1_REGS, (23), GPIO_PIN_HIGH);
mode = 1;
} else {
// Turn off LED
GPIOPinWrite(SOC_GPIO_1_REGS, (23), GPIO_PIN_LOW);
mode = 0;
}
/* *********** ISR TASKS END *********** */
/* Re-enable the DMTimer interrupt */
DMTimerIntEnable(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_EN_FLAG);
}
