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TDA4VEN-Q1: Regarding the delay issue of the LDC module

Ding Y
Intellectual 265 points
Part Number: TDA4VEN-Q1


Dear TI experts,

We have such an app: After the two-way camera images are processed by the Viss node, they are split by the Split node. One image is given to the LDC node 0 for processing, and the other image is given to the LDC nodes 1, 2, and 3 for processing. The four images output by the LDC are then cropped and scaled by the Mosaic node, and finally displayed. The delays of the four LDC nodes are shown in the figure. May I ask if the delay of the LDC hardware is the sum of the delays of the four nodes or the maximum value of the delays of the four nodes? Currently, the input and output dimensions of the four LDC nodes are both 1920x1536. Can the LDC hardware meet the 60fps requirement under such conditions? What is the upper limit of the computing power of the LDC hardware?

Best,

  • 0
    Intellectual 265 points

    In my understanding, the resources consumed by LDC are directly proportional to the number of pixels it outputs. Could you please tell me what is the maximum total number of pixels that can be output by the four LDC nodes if we want to maintain a frame rate of 60fps? We are using TDA4VEN and SDK 11.1.

  • 0 in reply to Ding Y
    TI__Guru 61970 points

    Hi Ding,

    Ding Y said:
    In my understanding, the resources consumed by LDC are directly proportional to the number of pixels it outputs.

    Yes, that is correct if the system has no DDR BW bottleneck.

    TDA4VEN VPAC may have a maximum frequency of 600MHz.
    We typically assume a 80% utility for about 480 MP/s.

    Ding Y said:
    Currently, the input and output dimensions of the four LDC nodes are both 1920x1536

    "1920*1536*4*60" is about 707 MP/s.
    That is beyond 480 MP/s estimate.

    In such a busy system, DDR BW may also be an issue and LDC may be slowed down further as it may have to read much larger input than 3MP per frame.