DS90UB948-Q1: 948 LVDS output has signal ,but no signal input from 947

Hi Roy,

I do not understand your question. When there is a video signal out of the 947 to the 948 there should be video signal on the LVDS lines of the 948.

Regards,

Michael W.

Hi Michael,

Sorry that I have typo. Please see below modification.

We just lock the 947 + 948 and we don't use internal patgen of 947 and also don't use external video signal, but we see there is signal on 948 LVDS output and clk1. 

May you help confirm that the state is normal or not? If you also expect that the 948 output should be no signal. How could we check the 947 and 948 and find the root cause? Thanks.

Roy

Hi Michael,

Please see the attached image.

G5 LVDS CLK1+ is our 947 TX board.

RX LVDS D2 is our 948 RX board data2 output.

RX LVDS CLK1 is our 948 RX board CLK1.

We expect seeing the right result when we shut down the 947TX board external clk. But we measured the three result showing as below, the middle and left one is abnormal to us. May we help let us know the possible root cause?

Roy

Hi Roy,

Can you send me the register dumps for the 947 and 948 when this issue is happening?

Hi Walker, 

Due to COVID, we couldn't go to LAB now. Could you let me know your idea first? Are you agree that right one is normal behavior? And may you let me know which register would you check first? thanks.

Roy

Hi Roy,

You should not see LVDS signal on the 948 if you are not inputting LVDS signal into the 947. I am not sure what the issue is that is why I want to check many registers on the 947 and 948. Can you check in the 947's registers if the "PCLK Detect" register is 1? What is "OSC Clock Source" set to on the 947?

Regards,

Michael W. 

Hi Michael,

We found that 0x0c[2] = 1 when issue occurred. But we had removed CLK+/- input. Do you have any idea for this issue?

Roy

Roy,

Can you check if the OSC_CLOCK_OUTPUT_ ENABLE__AUTO_CLOCK _EN bit in register 0x02 of the 948 is set?

For the 947 side clock can you also show CLK- in the scope shot as well as the differential voltage between P/N? It seems that 947 may be detecting noise on the clock lines as a valid clock. One thing you could try to verify that theory is to change 947 register 0x5C[4:3] = 11 to increase the stability threshold and avoid noise being picked up as a valid clock signal. 

Best Regards,

Casey