DP83867E: FLD strapping

Michael T Schneider

Part Number: DP83867E

Team,

We came across something in the datasheet that mentions the FLD strapping, but we can’t find the pins that are used. It says that this value is RO and defaults to the strapped value, but I can’t tell how this relates to any of the component pins. Do you have other documentation that covers this?

over 4 years ago

+1 Vikram Sharma over 4 years ago

TI__Genius 16030 points

Hello Michael,

This register is a carry forward from 64 pins version of the device. But 48 pin version (one you are referrring to) does not support this. In 48pin version please configure register "fld_cfg"

Regards,

Vikram

0 Michael T Schneider over 4 years ago in reply to Vikram Sharma

TI__Expert 3790 points

I assume we are using the 48 pin version. From the datasheet, this FLD_CFG register appears to default to “0”=normal operation. Although, reading this register appears to show that FLD is enabled. We are using the Xilinx Petalinux 2019.2 Driver for this part (Xilinx shows that it supports this device). I want to double check and make sure the part doesn’t enable this based on any of the other external pins. Also, are there any special things we need to put in the system-user.dtsi file for petalinux configuration?

0 Vikram Sharma over 4 years ago in reply to Michael T Schneider

TI__Genius 16030 points

Hello Michael,

Yes 48 pin does not support pin option for FLD. I am not sure if we can help with Xilinx configuration. Reference linux drivers for DP83867 is here : https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/dp83867.c

Regards,

Vikram

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DP83867E: FLD strapping